MB86941 Datasheet, PDF (21/49 Pages) Fujitsu Component Limited. – Peripheral LSI for SPARClite

(2) Clock signal (CLOCK)
Parameter
Clock cycle time
Clock “H” pulse width
Clock “L” pulse width
Clock rise time
Clock fall time
MB86941/942
Symbol
tCLK
tCLKH
tCLKL
tCLKR
tCLKF
(MB86941: VDD = 5 V ± 5%, TA = 0 to +70°C)
(MB86942: VDD = 3.3 V ± 0.15 V, TA = 0 to +70°C)
MB86941
Min.
Max.
MB86942
Unit
Min.
Max.
25
—
20
—
ns
9
—
8
—
ns
9
—
8
—
ns
—
4
—
2
ns
—
4
—
2
ns
CLOCK
tCLKH
tCLKF
tCLKL
tCLK
tCLKR
(3) MPU interface (Register read/write)
Parameter
AS# setup time
AS# hold time
CS# setup time
CS# hold time
RD/WR# setup time
RD/WR# hold time
RS < 5 : 0 > setup time
RS < 5 : 0 > hold time
READY1#, READY2# output delay time
READY1#, READY2# hold time
D < 15 : 0 > Output delay time at reading
D < 15 : 0 > Output hold time at reading
D < 15 : 0 > Input setup time at writing
D < 15 : 0 > Input hold time at writing
* : READY2# is available for MB86941.
(MB86941: VDD = 5 V ± 5%, TA = 0 to +70°C)
(MB86942: VDD = 3.3 V ± 0.15 V, TA = 0 to +70°C)
MB86941
MB86942
Symbol WSEL = “H” WSEL = “L”
Unit
Min. Max. Min. Max. Min. Max.
tASS
11 —
7
—
7
—
ns
tASH
0
—
0
—
2
—
ns
tCSS
8
—
5
—
7
—
ns
tCSH
0
—
0
—
2
—
ns
tRWS
13
—
9
—
7
—
ns
tRWH
0
—
0
—
2
—
ns
tRSS
8
—
5
—
7
—
ns
tRSH
0
—
0
—
2
—
ns
tRDYF
0
18
0
18
0
18
ns
tRDYH
5
20
5
20
5
20
ns
tODD
0
21
0
23
0 23
ns
tODH
5
25
5
25
5 20
ns
tIDS
11 —
7
—
7
—
ns
tIDH
0
—
0
—
0
—
ns
21