MB86941 Datasheet, PDF (4/49 Pages) Fujitsu Component Limited. – Peripheral LSI for SPARClite

MB86941/942
s BLOCK DIAGRAM
IRL < 3 : 0 >
÷2
CLOCK
RESET#
AS#
RD/WR#
CS#
RS < 5 : 0 >
D < 15 : 0 >
READY1#
READY2#*
WSEL
BIU
Bus
Interface
Unit
1 / 2 Clock
1 / 1 Clock
Reset
RCS#
A<1:0>
RDYOUT#
CS0# to CS3#
RE#
WE#
DS#
RCSTG
Read/Write
Chip Select
Timing
Generator
IPD < 15 : 0 >
IP
I/O Port
SICLK
SIRXD
SITXD
SIIRQ
DSR0#, CTS0#
RTS0#, DTR0#
TEMP0, TRDY0
TRNDT0
TCLK0#
RCLK0, RCVDT0
SYBRK0
RRDY0
SIO
Serial Data
Input
Output
SDTR0
Serial Data
Transmitter
Receiver
IRC
Interrupt
Request
Controller
PRS0
Prescaler
TM0
Timer
PRS1
Prescaler
TM1
Timer
TM2
Timer
TM3
Timer
DSR1#, CTS1#
RTS1#, DTR1#
TEMP1, TRDY1
TRNDT1
TCLK1#
RCLK1, RCVDT1
SYBRK1
RRDY1
SDTR1
Serial Data
Transmitter
Receiver
* : Only for MB86941. Open for MB86942.
4
Internal Data Bus
Internal Control Bus
IRQ1 to IRQ15
ACK0
PRSCK0
CLK0
IN0
OUT0
ACK1
PRSCK1
CLK1
IN1
OUT1
CLK2
IN2
OUT2
CLK3
IN3
OUT3