MB86941 Datasheet, PDF (10/49 Pages) Fujitsu Component Limited. – Peripheral LSI for SPARClite

MB86941/942
3. TIMER SIGNALS (16)
Pin symbol I/O Pin no.
Pin name
Description
CLK0
IN0
OUT0
I
61
Timer control signal pin
CLK0 : Timer Clock 0
These pins are used to input an external clock signal
I
62
to
to the timer.
CLK3 : Timer Clock 3 In external clock mode these signals are synchronized
O 65
with the internal clock.
CLK1
IN1
OUT1
I
71
IN0 : Timer Input 0
I
70
to
IN3 : Timer Input 3
O 67
Input pin for count operation control signals to the
timer
In MODE0 through MODE3, the input signal is a gate
signal. In MODE4, the pins input an external trigger
signal.
CLK2
IN2
OUT2
CLK3
IN3
OUT3
I
76
Timer output pin
I
77
The output waveform is determined by the mode
O
79
OUT0 : Timer Output 0 ^setting:
to
• Periodic signal waveform output
I
74 _{OUT3 : Timer Output 3}
• Square wave output
I
75
• One-shot pulse waveform output
O 80
At reset, an “L” level signal is output.
ACK0
ACK1
Prescaler asynchronous clock pin
I
63 Asynchronous Clock 0 ^{Input can be asynchronous with respect to the system}
clock signal input at the CLOCK pin.
If an external clock signal is selected by the PRS0 and
PRS1 registers, this signal can be used as a source
clock for the prescaler. The clock signal divided by the
I
69 Asynchronous Clock 1 prescaler is output at the PRSCK0, PRSCK1 pins.
If these pins are not used, they should be fixed at “L”
level.
PRSCK0
PRSCK1
O 64 Prescaler Clock Output 0 _{Prescaler clock output pin}
O 68 Prescaler Clock Output 1 ^{An “L” level signal is output at reset.}
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