MB86941 Datasheet, PDF (34/49 Pages) Fujitsu Component Limited. – Peripheral LSI for SPARClite

MB86941/942
• Receive Clock and Receive Data
Parameter
Receive clock period
Receive clock “H” width
Receive clock “L” width
Receive data setup time
Receive data hold time
Symbol
tRCK
tRCKHW
tRCKLW
tRDS
tRDH
(MB86941: VDD = 5 V ± 5%, TA = 0 to +70°C)
(MB86942: VDD = 3.3 V ± 0.15 V, TA = 0 to +70°C)
Syncroh mode, × 1 mode ×1/16, ×1/64 mode
Unit
Min.
Max.
Min.
Max.
62
—
8
—
tCLK
12
—
4
—
tCLK
7
—
4
—
tCLK
6
—
6
—
tCLK
6
—
6
—
tCLK
tCLK: See “(2) Clock Signals”.
RCLK
(× 1 mode,
Sync mode)
RCVDT
tRCKLW
tRCK
tRDS
tRCKHW
tRDH
tTCKDT
16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2
RCLK
(× 1/16 mode)
64 1 2 3
30 31 32 33 34 35
62 63 64 1 2
RCLK
(× 1/64 mode)
⋅⋅⋅⋅⋅
⋅⋅⋅⋅⋅
tRCKLW
tRCK
34