MB86941 Datasheet, PDF (28/49 Pages) Fujitsu Component Limited. – Peripheral LSI for SPARClite

MB86941/942
• Timer (at external clock mode)
Parameter
Timer input clock “H” level width
Timer input clock “L” level width
GATE signal (IN pin) setup time (for CLKx)
GATE signal (IN pin) hold time (for CLKx)
tCLK: See “(2) Clock Signals”.
CLKx
tTCKH
tTCKL
INx (as IN pin of EVENT set “L”)
INx (as IN pin of EVENT set “H”)
• Timer output 1
Parameter
OUT output delay time (for CLOCK)
(MB86941: VDD = 5 V ± 5%, TA = 0 to +70°C)
(MB86942: VDD = 3.3 V ± 0.15 V, TA = 0 to +70°C)
Value
Symbol
Unit
Min.
Max.
tTCKH
3
—
tCLK
tTCKL
3
—
tCLK
tGS
10
—
ns
tGH
0
—
ns
tGS
tGH
(MB86941: VDD = 5 V ± 5%, TA = 0 to +70°C)
(MB86942: VDD = 3.3 V ± 0.15 V, TA = 0 to +70°C)
Value
Symbol
Unit
Min.
Max.
tOUTD1
—
30
ns
CLOCK
OUTx
tOUTD1
28