MB86941 Datasheet, PDF (7/49 Pages) Fujitsu Component Limited. – Peripheral LSI for SPARClite

MB86941/942
1. MPU INTERFACE SIGNALS (34/33)
Pin symbol I/O Pin no.
Pin name
RESET#
I 118 Reset
CLOCK
I 119 Clock
AS#
I 120 Address Strobe
RD/WR#
CS#
RS0
RS1
RS2
RS3
RS4
RS5
READY1#
I 121 Read/Write
I 122 Chip Select
I 135 Register Select 0
I 134 Register Select 1
I 132 Register Select 2
I 131 Register Select 3
I 130 Register Select 4
I 133 Register Select 5
O 20 Ready 1
READY2#
O
17 Ready 2
WSEL
I 113 Wait Select
Description
Reset input pin
Input an “L” signal to this pin to reset the chip.
System clock input pin
The chip contains some modules that use the clock
signal from this pin (not divided), and other modules
that use the clock signal divided in half.
Clock not divided: BIU, RCSTG, IP
Clock divided: IRC, PRS0, PRS1, TM0 to TM3,
SDTR0, SDTR1, SIO
Address strobe input pin
Input an “L” signal to this pin to determine register
access according to the signals input to the RS<5:0>,
CS#, and RD/WR# pins.
Read/write input pin
Input an “H” signal to designate a read cycle, or an “L”
signal to designate a write cycle.
Chip select input pin
Register select input pin
The combination of input signals to the RS<5:0> and
CS# pins determines which register is accessed.
The RS5 pin has internal pull-down resistance
(MB86941 only).
Data ready output pin
MB86941: Open drain output with 12mA “L” drive
capability. Drives an “H” level signal for 3ns
before going to High-Z state.
MB86942: Normal output. READY2# signal deleted. If
the READY generator circuit in the MPU is
used, it is not necessary to connect this pin
to the MPU.
Wait select input pin
Input to this pin determines the interface timing with
the MPU.
Fix “L” to set register read/write access to 3 cycles, or
fix “H” to set register read/write access to 2 cycles.
This pin has internal pull-up resistance (MB86941
only).
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