MB86941 Datasheet, PDF (31/49 Pages) Fujitsu Component Limited. – Peripheral LSI for SPARClite

• DTR#, RTS#, TRDY
Parameter
Delay time from register write to DTR# output
Delay time from register write to RTS# output
Delay time from register write to TRDY output
tCLK: See “(2) Clock Signals”.
MB86941/942
(MB86941: VDD = 5 V ± 5%, TA = 0 to +70°C)
(MB86942: VDD = 3.3 V ± 0.15 V, TA = 0 to +70°C)
Value
Symbol
Unit
Min.
Max.
tDTROD
0
40
tCLK
tRTSOD
0
40
tCLK
tTRDYOD
0
100
ns
CLOCK
AS#
CS#
RS < 5 : 0 >
RD/WR#
D < 15 : 0 >
READY1#
READY2#*
DSR#,
RTS#
High-Z
MB86942: “H” level output
TRDY
* : Only for MB86941.
Register write
High-Z
MB86942: “H” level output
tTRDYOD
tRRDYL, tDTROD
31