MB86941 Datasheet, PDF (27/49 Pages) Fujitsu Component Limited. – Peripheral LSI for SPARClite

MB86941/942
(5) Prescaler timer
• Prescaler input
Parameter
Prescaler input clock cycle time*
Prescaler input clock “H” level width*
Prescaler input clock “L” level width*
Prescaler input clock rise time*
Prescaler input clock fall time*
Symbol
tACK
tACHW
tACLW
tACR
tACF
(MB86941: VDD = 5 V ± 5%, TA = 0 to +70°C)
(MB86942: VDD = 3.3 V ± 0.15 V, TA = 0 to +70°C)
MB86941
Min.
Max.
MB86942
Unit
Min.
Max.
50
—
40
—
ns
22
—
15
—
ns
22
—
15
—
ns
—
5
—
5
ns
—
5
—
5
ns
* : Applied in prescaler external clock mode. When the prescaler output is used as a timer signal, the timer input
clock requirements must be met.
ACLK0,
ACLK1
tACHW
tACF
tACLW
tACK
tACR
• Prescaler output
Parameter
Prescaler output “L” level width*^1, *³
Prescaler output “H” level width*^1, *³
Prescaler output “L” level width*^2, *³
Prescaler output “H” level width*^2, *³
(MB86941: VDD = 5 V ± 5%, TA = 0 to +70°C)
(MB86942: VDD = 3.3 V ± 0.15 V, TA = 0 to +70°C)
Symbol
Standard Value
Unit
tPSCLW
1
tPCK*⁴
tPSCHW
N–1
tPCK*⁴
tPSCLW
N ⋅ 2^{M – 1}
tPCK*⁴
tPSCHW
N ⋅ 2^{M – 1}
tPCK*⁴
*1: Applied when the prescaler register SELECT field is set to “0.”
N: Value set in the prescaler register PRESCALE VALUE field
*2: Applied when the prescaler register SELECT field is set to any value other than “0.”
M: Value set in the prescaler register SELECT field.
N: Value set in the prescaler register PRESCALE VALUE field.
*3: When the prescaler register SELECT field is set to “0,” the PRSCKx output is fixed at “L” level.
*4: tPCK has the following prescaler input clock period.
Internal clock mode: tPCK = 2 ⋅ tCLK (For tCLK, see “(2) Clock Signals”)
External clock mode: tPCK = tACK (For tACK, see “(5) Prescaler Timer Unit/Prescaler Input”)
tPSCLW
tPSCHW
PRSCK0,
PRSCK1
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