MB86941 Datasheet, PDF (35/49 Pages) Fujitsu Component Limited. – Peripheral LSI for SPARClite

MB86941/942
• SYBRK Signal Timing for External Synchronous mode
(MB86941: VDD = 5 V ± 5%, TA = 0 to +70°C)
(MB86942: VDD = 3.3 V ± 0.15 V, TA = 0 to +70°C)
Parameter
Value
Symbol
Unit
Min.
Max.
SYBRK setup time (for RCLK)
tBRKS
0
—
tCLK
SYBRK hold time (for RCLK)
tBRKH
10
—
tCLK
tCLK: See “(2) Clock Signals”.
RCLK
SYBRK
tBRKH
tBRKS
• Transmit and Receive Control Signal Timing
Parameter
Delay time from TCLK# rising (last bit) to TRDY rising
Delay time from TCLK# rising (last bit) to TEMP rising
Delay time from RCLK rising (last bit) to RRDY rising
Detection time from RCLK rising (last bit) to internal
SYNC (SYBRK pin)
Detection time RCLK rising (last bit) to internal SYNC
(status data buffer register)
tCLK: See “(2) Clock Signals”.
(MB86941: VDD = 5 V ± 5%, TA = 0 to +70°C)
(MB86942: VDD = 3.3 V ± 0.15 V, TA = 0 to +70°C)
Value
Symbol
Unit
Min.
Max.
tTCKRDY
—
36
tCLK
tTCKEMP
—
24
tCLK
tRCKRDY
—
35
tCLK
tSYCD1
—
62
tCLK
tSYCD2
—
70
tCLK
35