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MC908AP16CFAE Datasheet, PDF (97/324 Pages) Freescale Semiconductor, Inc – Table of Contents | |||
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Chapter 7
System Integration Module (SIM)
7.1 Introduction
This section describes the system integration module (SIM). Together with the CPU, the SIM controls all
MCU activities. A block diagram of the SIM is shown in Figure 7-1. Figure 7-2 is a summary of the SIM
input/output (I/O) registers. The SIM is a system state controller that coordinates CPU and exception
timing. The SIM is responsible for:
⢠Bus clock generation and control for CPU and peripherals:
â Stop/wait/reset/break entry and recovery
â Internal clock control
⢠Master reset control, including power-on reset (POR) and COP timeout
⢠Interrupt control:
â Acknowledge timing
â Arbitration control timing
â Vector address generation
⢠CPU enable/disable timing
⢠Modular architecture expandable to 128 interrupt sources
Table 7-1 shows the internal signal names used in this section.
Signal Name
ICLK
CGMXCLK
CGMVCLK, CGMPCLK
CGMOUT
IAB
IDB
PORRST
IRST
R/W
Table 7-1. Signal Name Conventions
Description
Internal oscillator clock
Selected oscillator clock from oscillator module
PLL output and the divided PLL output
CGMPCLK-based or oscillator-based clock output from CGM module
(Bus clock = CGMOUT ÷ 2)
Internal address bus
Internal data bus
Signal from the power-on reset module to the SIM
Internal reset signal
Read/write signal
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
97
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