MC908AP16CFAE Datasheet, PDF (87/324 Pages) Freescale Semiconductor, Inc – Table of Contents

I/O Signals
6.3.9 CGM External Connections
In its typical configuration, the CGM requires up to four external components.
Figure 6-3 shows the external components for the PLL:
• Bypass capacitor, C_BYP
• Filter network
Care should be taken with PCB routing in order to minimize signal cross talk and noise. (See 6.8
Acquisition/Lock Time Specifications for routing information, filter network and its effects on PLL
performance.)
MCU
CGMXFC
1 kΩ
0.22 µF
10 nF
V_SSA
V_DDA
V_DD
C_BYP
0.1 µF
Note: Filter network in box can be replaced with a 0.47µF capacitor, but will degrade stability.
Figure 6-3. CGM External Connections
6.4 I/O Signals
The following paragraphs describe the CGM I/O signals.
6.4.1 External Filter Capacitor Pin (CGMXFC)
The CGMXFC pin is required by the loop filter to filter out phase corrections. An external filter network is
connected to this pin. (See Figure 6-3.)
NOTE
To prevent noise problems, the filter network should be placed as close to
the CGMXFC pin as possible, with minimum routing distances and no
routing of other signals across the network.
6.4.2 PLL Analog Power Pin (V_DDA)
V_DDA is a power pin used by the analog portions of the PLL. Connect the V_DDA pin to the same voltage
potential as the V_DD pin.
NOTE
Route V_DDA carefully for maximum noise immunity and place bypass
capacitors as close as possible to the package.
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
87