MC908AP16CFAE Datasheet, PDF (293/324 Pages) Freescale Semiconductor, Inc – Table of Contents

Chapter 21
Break Module (BRK)
21.1 Introduction
This section describes the break module. The break module can generate a break interrupt that stops
normal program flow at a defined address to enter a background program.
21.2 Features
Features of the break module include:
• Accessible input/output (I/O) registers during the break interrupt
• CPU-generated break interrupts
• Software-generated break interrupts
• COP disabling during break interrupts
Addr.
Register Name
$FE00
Read:
SIM Break Status Register
(SBSR)
Write:
Reset:
$FE03
SIM Break Flag Control ^Read:
Register Write:
(SBFCR) _Reset:
Break Address ^Read:
$FE0C
Register High Write:
(BRKH) _Reset:
$FE0D
Break Address ^Read:
Register Low Write:
(BRKL) _Reset:
$FE0E
Break Status and Control ^Read:
Register Write:
(BRKSCR) _Reset:
Note: Writing a logic 0 clears BW.
Bit 7
R
BCFE
0
Bit 15
0
Bit 7
0
BRKE
0
6
5
R
R
R
R
14
13
0
0
6
5
0
0
0
BRKA
0
0
= Unimplemented
4
3
2
R
R
R
R
R
R
12
11
10
0
0
0
4
3
2
0
0
0
0
0
0
0
0
0
R = Reserved
Figure 21-1. Break Module I/O Register Summary
1
Bit 0
SBSW
R
Note
0
R
R
9
Bit 8
0
0
1
Bit 0
0
0
0
0
0
0
21.3 Functional Description
When the internal address bus matches the value written in the break address registers, the break module
issues a breakpoint signal to the CPU. The CPU then loads the instruction register with a software
interrupt instruction (SWI) after completion of the current CPU instruction. The program counter vectors
to $FFFC and $FFFD ($FEFC and $FEFD in monitor mode).
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
291