MC908AP16CFAE Datasheet, PDF (86/324 Pages) Freescale Semiconductor, Inc – Table of Contents

Clock Generator Module (CGM)
CGMVCLK
8.0 MHz
9.8304 MHz
10.0 MHz
16 MHz
19.6608 MHz
20 MHz
29.4912 MHz
32 MHz
32 MHz
32 MHz
32 MHz
Table 6-1. Numeric Examples
CGMPCLK
8.0 MHz
9.8304 MHz
10.0 MHz
16 MHz
19.6608 MHz
20 MHz
29.4912 MHz
32 MHz
16 MHz
8 MHz
4 MHz
f_BUS
2.0 MHz
2.4576 MHz
2.5 MHz
4.0 MHz
4.9152 MHz
5.0 MHz
7.3728 MHz
8.0 MHz
4.0 MHz
2.0 MHz
1.0 MHz
f_RCLK
R N PE L
32.768 kHz 1 F5 0 0 40
32.768 kHz 1 12C 0 1 27
32.768 kHz 1 132 0 1 28
32.768 kHz 1 1E9 0 1 40
32.768 kHz 1 258 0 2 27
32.768 kHz 1 263 0 2 28
32.768 kHz 1 384 0 2 3B
32.768 kHz 1 3D1 0 2 40
32.768 kHz 1 1E9 1 2 40
32.768 kHz 1 F5 2 2 40
32.768 kHz 1 7B 3 2 40
6.3.7 Special Programming Exceptions
The programming method described in 6.3.6 Programming the PLL does not account for three possible
exceptions. A value of 0 for R, N, or L is meaningless when used in the equations given. To account for
these exceptions:
• A 0 value for R or N is interpreted exactly the same as a value of 1.
• A 0 value for L disables the PLL and prevents its selection as the source for the base clock.
(See 6.3.8 Base Clock Selector Circuit.)
6.3.8 Base Clock Selector Circuit
This circuit is used to select either the oscillator clock, CGMXCLK, or the divided VCO clock, CGMPCLK,
as the source of the base clock, CGMOUT. The two input clocks go through a transition control circuit that
waits up to three CGMXCLK cycles and three CGMPCLK cycles to change from one clock source to the
other. During this time, CGMOUT is held in stasis. The output of the transition control circuit is then
divided by two to correct the duty cycle. Therefore, the bus clock frequency, which is one-half of the base
clock frequency, is one-fourth the frequency of the selected clock (CGMXCLK or CGMPCLK).
The BCS bit in the PLL control register (PCTL) selects which clock drives CGMOUT. The divided VCO
clock cannot be selected as the base clock source if the PLL is not turned on. The PLL cannot be turned
off if the divided VCO clock is selected. The PLL cannot be turned on or off simultaneously with the
selection or deselection of the divided VCO clock. The divided VCO clock also cannot be selected as the
base clock source if the factor L is programmed to a 0. This value would set up a condition inconsistent
with the operation of the PLL, so that the PLL would be disabled and the oscillator clock would be forced
as the source of the base clock.
MC68HC908AP Family Data Sheet, Rev. 4
86
Freescale Semiconductor