MC908AP16CFAE Datasheet, PDF (239/324 Pages) Freescale Semiconductor, Inc – Table of Contents

MMIIC I/O Registers
MMRW — MMIIC Master Read/Write
This bit is transmitted out as bit 0 of the calling address when the module sets the MMAST bit to enter
master mode. The MMRW bit determines the transfer direction of the data bytes that follows. When it
is "1", the module is in master receive mode. When it is "0", the module is in master transmit mode.
Reset clears this bit.
1 = Master mode receive
0 = Master mode transmit
MMCRCEF — MMIIC CRC Error Flag
This flag is set when a CRC error is detected, and cleared when no CRC error is detected. The
MMCRCEF is only meaningful after receiving a PEC data. This flag is unaffected by reset.
1 = CRC error detected on PEC byte
0 = No CRC error detected on PEC byte
14.6.4 MMIIC Status Register (MMSR)
Address: $004B
Bit 7
Read: MMRXIF
Write: 0
Reset: 0
6
5
MMTXIF MMATCH
0
0
0
= Unimplemented
4
MMSRW
0
3
2
1
MMRXAK MMCRCBF MMTXBE
1
0
1
Bit 0
MMRXBF
0
Figure 14-7. MMIIC Status Register (MMSR)
MMRXIF — MMIIC Receive Interrupt Flag
This flag is set after the data receive register (MMDRR) is loaded with a new received data. Once the
MMDRR is loaded with received data, no more received data can be loaded to the MMDRR register
until the CPU reads the data from the MMDRR to clear MMRXBF flag. MMRXIF generates an interrupt
request to CPU if the MMIEN bit in MMCR is also set. This bit is cleared by writing "0" to it or by reset;
or when the MMEN = 0.
1 = New data in data receive register (MMDRR)
0 = No data received
MMTXIF — MMIIC Transmit Interrupt Flag
This flag is set when data in the data transmit register (MMDTR) is downloaded to the output circuit,
and that new data can be written to the MMDTR. MMTXIF generates an interrupt request to CPU if the
MMIEN bit in MMCR is also set. This bit is cleared by writing "0" to it or when the MMEN = 0.
1 = Data transfer completed
0 = Data transfer in progress
MMATCH — MMIIC Address Match Flag
This flag is set when the received data in the data receive register (MMDRR) is a calling address which
matches with the address or its extended addresses (MMEXTAD = 1) specified in the address register
(MMADR). The MMATCH flag is set at the 9th clock of the calling address and will be cleared on the
9th clock of the next receiving data. Note: slave transmits do not clear MMATCH.
1 = Received address matches MMADR
0 = Received address does not match
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
237