MC908AP16CFAE Datasheet, PDF (120/324 Pages) Freescale Semiconductor, Inc – Table of Contents

Monitor ROM (MON)
8.3.2 Data Format
Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format.
Transmit and receive baud rates must be identical.
START
BIT BIT 0
BIT 1
BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7
Figure 8-3. Monitor Data Format
NEXT
START
STOP BIT
BIT
8.3.3 Break Signal
A start bit (logic 0) followed by nine logic 0 bits is a break signal. When the monitor receives a break signal,
it drives the PTA0 pin high for the duration of two bits and then echoes back the break signal.
MISSING STOP BIT
2-STOP BIT DELAY BEFORE ZERO ECHO
01234567
01234567
Figure 8-4. Break Transaction
8.3.4 Baud Rate
The communication baud rate is controlled by the crystal frequency and the state of the PTB0 pin (when
IRQ1 is set to V_TST) upon entry into monitor mode. When PTB0 is high, the divide by ratio is 1024. If the
PTB0 pin is at logic 0 upon entry into monitor mode, the divide by ratio is 512.
If monitor mode was entered with V_DD on IRQ1, then the divide by ratio is set at 1024, regardless of PTB0.
This condition for monitor mode entry requires that the reset vector is blank.
Table 8-3 lists external frequencies required to achieve a standard baud rate of 9600 BPS. Other
standard baud rates can be accomplished using proportionally higher or lower frequency generators. If
using a crystal as the clock source, be aware of the upper frequency limit that the internal clock module
can handle.
Table 8-3. Monitor Baud Rate Selection
External
Frequency
4.9152 MHz
9.8304 MHz
9.8304 MHz
32.768 kHz
IRQ1
V_TST
V_TST
V_DD
V_SS
PTB0
0
1
X
X
Internal
Frequency
2.4576 MHz
2.4576 MHz
2.4576 MHz
2.4576 MHz
Baud Rate
(BPS)
9600
9600
9600
9600
MC68HC908AP Family Data Sheet, Rev. 4
120
Freescale Semiconductor