MC908AP16CFAE Datasheet, PDF (50/324 Pages) Freescale Semiconductor, Inc – Table of Contents

Configuration & Mask Option Registers (CONFIG & MOR)
3.2 Functional Description
The configuration registers and the mask option register are used in the initialization of various options.
These two types of registers are configured differently:
• Configuration registers — Write-once registers after reset
• Mask option register — FLASH register (write by programming)
The configuration registers can be written once after each reset. All of the configuration register bits are
cleared during reset. Since the various options affect the operation of the MCU, it is recommended that
these registers be written immediately after reset. The configuration registers are located at $001D and
$001F. The configuration registers may be read at anytime.
NOTE
The CONFIG registers are not in the FLASH memory but are special
registers containing one-time writable latches after each reset. Upon a
reset, the CONFIG registers default to predetermined settings as shown in
Figure 3-2 and Figure 3-3.
The mask option register (MOR) is used for selecting one of the three clock options for the MCU. The
MOR is a byte located in FLASH memory, and is written to by a FLASH programming routine.
3.3 Configuration Register 1 (CONFIG1)
Address: $001F
Bit 7
6
5
4
3
2
1
Read:
COPRS LVISTOP LVIRSTD LVIPWRD LVIREGD SSREC
Write:
STOP
Reset: 0
0
0
0
0
0
0
Figure 3-2. Configuration Register 1 (CONFIG1)
Bit 0
COPD
0
COPRS — COP Rate Select Bit
COPRS selects the COP time out period. Reset clears COPRS. (See Chapter 19 Computer Operating
Properly (COP).)
1 = COP time out period = 2¹³ – 2⁴ ICLK cycles
0 = COP time out period = 2¹⁸ – 2⁴ ICLK cycles
LVISTOP — LVI Enable in Stop Mode Bit
When the LVIPWRD or LVIREGD bit is clear, setting the LVISTOP bit enables the LVI to operate
during stop mode. Reset clears LVISTOP. (See Chapter 20 Low-Voltage Inhibit (LVI).)
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
NOTE
If LVISTOP=0, set LVIRSTD=1 before entering stop mode.
LVIRSTD — LVI Reset Disable Bit
LVIRSTD disables the reset signal from the LVI module. (See Chapter 20 Low-Voltage Inhibit (LVI).)
1 = LVI module resets disabled
0 = LVI module resets enabled
MC68HC908AP Family Data Sheet, Rev. 4
50
Freescale Semiconductor