MC908AP16CFAE Datasheet, PDF (290/324 Pages) Freescale Semiconductor, Inc – Table of Contents

Low-Voltage Inhibit (LVI)
an LVI reset occurs, the MCU remains in reset until V_DD rises above V_TRIPR1 and V_REG rises above
V_TRIPR2, which causes the MCU to exit reset. The output of the comparator controls the state of the
LVIOUT flag in the LVI status register (LVISR).
An LVI reset also drives the RST pin low to provide low-voltage protection to external peripheral devices.
V_DD
STOP INSTRUCTION
LVISTOP
FROM CONFIG1
LVIPWRD
FROM CONFIG1
LOW V_DD
DETECTOR
V_DD > V_TRIPR1 = 0
V_DD ≤ V_TRIPF1 = 1
LOW V_REG
DETECTOR
V_REG > V_TRIPR2 = 0
V_REG ≤ V_TRIPF2 = 1
FROM CONFIG1
LVIREGD
FROM CONFIG1
LVIRSTD
LVIOUT
TO LVISR
LVI RESET
V_REG
FROM CONFIG1
LVISTOP
STOP INSTRUCTION
Figure 20-2. LVI Module Block Diagram
20.3.1 Low V_DD Detector
The low V_DD detector circuit monitors the V_DD voltage and forces a LVI reset when the V_DD voltage falls
below the trip voltage, V_TRIPF1. The V_DD LVI circuit can be disabled by the setting the LVIPWRD bit in
CONFIG1 register.
20.3.2 Low V_REG Detector
The low V_REG detector circuit monitors the V_REG voltage and forces a LVI reset when the V_REG voltage
falls below the trip voltage, V_TRIPF2. The V_REG LVI circuit can be disabled by the setting the LVIREGD bit
in CONFIG1 register.
20.3.3 Polled LVI Operation
In applications that can operate at V_DD levels below the V_TRIPF1 level, software can monitor V_DD by polling
the LVIOUT bit. In the CONFIG1 register, the LVIPWRD bit must be at logic 0 to enable the LVI module,
and the LVIRSTD bit must be at logic 1 to disable LVI resets.
MC68HC908AP Family Data Sheet, Rev. 4
288
Freescale Semiconductor