MC9S08GB60A Datasheet, PDF (96/302 Pages) Freescale Semiconductor, Inc – HCS08 Microcontrollers

Chapter 6 Parallel Input/Output
R
W
Reset
7
PTDSE7
0
6
PTDSE6
5
PTDSE5
4
PTDSE4
3
PTDSE3
2
PTDSE2
1
PTDSE1
0
0
0
0
0
0
Figure 6-23. Slew Rate Control Enable for Port D (PTDSE)
0
PTDSE0
0
Table 6-15. PTDSE Field Descriptions
Field
Description
7:0
PTDSE[7:0]
Slew Rate Control Enable for Port D Bits — For port D pins that are outputs, these read/write control bits
determine whether the slew rate controlled outputs are enabled. For port D pins that are configured as inputs,
these bits are ignored.
0 Slew rate control disabled.
1 Slew rate control enabled.
R
W
Reset
7
PTDDD7
0
6
PTDDD6
5
PTDDD5
4
PTDDD4
3
PTDDD3
2
PTDDD2
0
0
0
0
0
Figure 6-24. Data Direction for Port D (PTDDD)
1
PTDDD1
0
0
PTDDD0
0
Table 6-16. PTDDD Field Descriptions
Field
Description
7:0
Data Direction for Port D Bits — These read/write bits control the direction of port D pins and what is read for
PTDDD[7:0] PTDD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port D bit n and PTDD reads return the contents of PTDDn.
MC9S08GB60A Data Sheet, Rev. 2
96
Freescale Semiconductor