MC9S08GB60A Datasheet, PDF (237/302 Pages) Freescale Semiconductor, Inc – HCS08 Microcontrollers

Analog-to-Digital Converter (S08ATDV3)
Table 14-6. ATD1SC Field Descriptions
Field
7
CCF
6
ATDIE
5
ATDCO
4:0
ATDCH
Description
Conversion Complete Flag — The CCF is a read-only bit which is set each time a conversion is complete. The
CCF bit is cleared whenever the ATD1SC register is written. It is also cleared whenever the result registers,
ATD1RH or ATD1RL, are read.
0 Current conversion is not complete.
1 Current conversion is complete.
ATD Interrupt Enabled — When this bit is set, an interrupt is generated upon completion of an ATD conversion.
At this time, the result registers contain the result data generated by the conversion. The interrupt will remain
pending as long as the conversion complete flag CCF is set. If the ATDIE bit is cleared, then the CCF bit must
be polled to determine when the conversion is complete. Note that system reset clears pending interrupts.
0 ATD interrupt disabled.
1 ATD interrupt enabled.
ATD Continuous Conversion — When this bit is set, the ATD will convert samples continuously and update the
result registers at the end of each conversion. When this bit is cleared, only one conversion is completed between
writes to the ATD1SC register.
0 Single conversion mode.
1 Continuous conversion mode.
Analog Input Channel Select — This field of bits selects the analog input channel whose signal is sampled and
converted to digital codes. Table 14-7 lists the coding used to select the various analog input channels.
Table 14-7. Analog Input Channel Select Coding
ATDCH
00
01
02
03
04
05
06
07
08–1D
1E
1F
Analog Input Channel
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
Reserved (default to V_REFL)
V_REFH
V_REFL
14.6.3 ATD Result Data (ATD1RH, ATD1RL)
For left-justified mode, result data bits 9–2 map onto bits 7–0 of ATD1RH, result data bits 1 and 0 map
onto ATD1RL bits 7 and 6, where bit 7 of ATD1RH is the most significant bit (MSB).
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor
237