MC9S08GB60A Datasheet, PDF (213/302 Pages) Freescale Semiconductor, Inc – HCS08 Microcontrollers

13.3.4 IIC Status Register (IIC1S)
Inter-Integrated Circuit (S08IICV1)
R
W
Reset
Field
7
TCF
6
IAAS
5
BUSY
4
ARBL
2
SRW
1
IICIF
0
RXAK
7
6
5
4
3
2
1
0
TCF
BUSY
0
SRW
RXAK
IAAS
ARBL
IICIF
1
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 13-6. IIC Status Register (IIC1S)
Table 13-5. IIC1S Register Field Descriptions
Description
Transfer Complete Flag — This bit is set on the completion of a byte transfer. Note that this bit is only valid
during or immediately following a transfer to the IIC module or from the IIC module.The TCF bit is cleared by
reading the IIC1D register in receive mode or writing to the IIC1D in transmit mode.
0 Transfer in progress.
1 Transfer complete.
Addressed as a Slave — The IAAS bit is set when the calling address matches the programmed slave address.
Writing the IIC1C register clears this bit.
0 Not addressed.
1 Addressed as a slave.
Bus Busy — The BUSY bit indicates the status of the bus regardless of slave or master mode. The BUSY bit is
set when a START signal is detected and cleared when a STOP signal is detected.
0 Bus is idle.
1 Bus is busy.
Arbitration Lost — This bit is set by hardware when the arbitration procedure is lost. The ARBL bit must be
cleared by software, by writing a one to it.
0 Standard bus operation.
1 Loss of arbitration.
Slave Read/Write — When addressed as a slave the SRW bit indicates the value of the R/W command bit of
the calling address sent to the master.
0 Slave receive, master writing to slave.
1 Slave transmit, master reading from slave.
IIC Interrupt Flag — The IICIF bit is set when an interrupt is pending. This bit must be cleared by software, by
writing a one to it in the interrupt routine. One of the following events can set the IICIF bit:
• One byte transfer completes
• Match of slave address to calling address
• Arbitration lost
0 No interrupt pending.
1 Interrupt pending.
Receive Acknowledge — When the RXAK bit is low, it indicates an acknowledge signal has been received after
the completion of one byte of data transmission on the bus. If the RXAK bit is high it means that no acknowledge
signal is detected.
0 Acknowledge received.
1 No acknowledge received.
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor
213