MC9S08GB60A Datasheet, PDF (110/302 Pages) Freescale Semiconductor, Inc – HCS08 Microcontrollers

Internal Clock Generator (S08ICGV2)
In this state, the FLL loop is open. The DCO is on, and the output clock signal ICGOUT frequency is given
by f_ICGDCLK / R. The ICGDCLK frequency can be varied from 8 MHz to 40 MHz by writing a new value
into the filter registers (ICGFLTU and ICGFLTL). This is the only mode in which the filter registers can
be written.
If this mode is entered due to a reset, f_ICGDCLK will default to f_{Self_reset} which is nominally 8 MHz. If this
mode is entered from FLL engaged internal, f_ICGDCLK will maintain the previous frequency. If this mode
is entered from FLL engaged external (either by programming CLKS or due to a loss of external reference
clock), f_ICGDCLK will maintain the previous frequency, but ICGOUT will double if the FLL was unlocked.
If this mode is entered from off mode, f_ICGDCLK will be equal to the frequency of ICGDCLK before
entering off mode. If CLKS bits are set to 01 or 11 coming out of the Off state, the ICG enters this mode
until ICGDCLK is stable as determined by the DCOS bit. Once ICGDCLK is considered stable, the ICG
automatically closes the loop by switching to FLL engaged (internal or external) as selected by the CLKS
bits.
CLKST
CLKS
RFD
REFERENCE
DIVIDER (/7)
RANGE
MFD
ICGIRCLK
FLT
CLOCK
SELECT
CIRCUIT
ICGDCLK
REDUCED
FREQUENCY
ICGOUT
DIVIDER (R)
SUBTRACTOR
DIGITAL
LOOP
FILTER
CLKST
DIGITALLY ^1x
CONTROLLED
OSCILLATOR _2x
FLL ANALOG
OVERFLOW
COUNTER ENABLE
RANGE
LOCK AND
LOSS OF CLOCK
DETECTOR
PULSE
COUNTER
ICG2DCLK
RESET AND
INTERRUPT
CONTROL
FREQUENCY-
LOCKED
LOOP (FLL)
IRQ
RESET
DCOS LOCK LOLS LOCS ERCS LOCD
ICGIF LOLRE LOCRE
Figure 7-6. Detailed Frequency-Locked Loop Block Diagram
MC9S08GB60A Data Sheet, Rev. 2
110
Freescale Semiconductor