MC9S08GB60A Datasheet, PDF (229/302 Pages) Freescale Semiconductor, Inc – HCS08 Microcontrollers

Analog-to-Digital Converter (S08ATDV3)
• ATD input capacitance (C_AIN – maximum value 50 pF) — This is the internal capacitance of the
ATD sample and hold circuit. This capacitance varies with temperature, voltage, and process
variation but a worst case number is necessary to compute worst case sample error.
• ATD conversion clock frequency (f_ATDCLK – maximum value 2 MHz) — This is the frequency of
the clock input to the ATD and is dependent on the bus clock frequency and the ATD prescaler.
This frequency determines the width of the sample window, which is 14 ATDCLK cycles.
• Input sample frequency (f_SAMP – see Appendix A, “Electrical Characteristics”) — This is the
frequency that a given input is sampled.
• Delta-input sample voltage (ΔV_SAMP) — This is the difference between the current input voltage
(intended for conversion) and the previously sampled voltage (which may be from a different
channel). In non-continuous convert mode, this is assumed to be the greater of (V_REFH – V_AIN) and
(V_AIN – V_REFL). In continuous convert mode, 5 LSB should be added to the known difference to
account for leakage and other losses.
• Delta-analog input voltage (ΔV_AIN) — This is the difference between the current input voltage and
the input voltage during the last conversion on a given channel. This is based on the slew rate of
the input.
In cases where there is no external filtering capacitance, the sampling error is determined by the number
of time constants of charging and the change in input voltage relative to the resolution of the ATD:
# of time constants (τ) = (14 / f_ATDCLK) / ((R_AS + R_AIN) * C_AIN)
sampling error in LSB (E_S) = 2^N * (ΔV_SAMP / (V_REFH - V_REFL)) * e^−τ
The maximum sampling error (assuming maximum change on the input voltage) will be:
Eqn. 14-1
E_S = (3.6/3.6) * e^{–(14/((7 k + 10 k) * 50 p * 2 M))} * 1024 = 0.271 LSB
Eqn. 14-2
In the case where an external filtering capacitance is applied, the sampling error can be reduced based on
the size of the source capacitor (C_AS) relative to the analog input capacitance (C_AIN). Ignoring the analog
source impedance (R_AS), C_AS will charge C_AIN to a value of:
E_S = 2^N * (ΔV_SAMP / (V_REFH – V_REFL)) * (C_AIN / (C_AIN + C_AS))
Eqn. 14-3
In the case of a 0.1 μF C_AS, a worst case sampling error of 0.5 LSB is achieved regardless of R_AS.
However, in the case of repeated conversions at a rate of f_SAMP, R_AS must re-charge C_AS. This recharge is
continuous and controlled only by R_AS (not R_AIN), and reduces the overall sampling error to:
+
(ΔV_SAMP
/
(V_REFH
E_S = 2^N * {(ΔV_AIN / (V_REFH – V_REFL))
- V_REFL)) * Min[(C_AIN / (C_AIN + C_AS)),
* e^{−(1 / (fSAMP * RAS *}
e^{−(1 / (fATDCLK * (RAS}
CAS )
+ RAIN)
*
CAIN
)_]}
Eqn. 14-4
This is a worst case sampling error which does not account for R_AS recharging the combination of C_AS
and C_AIN during the sample window. It does illustrate that high values of R_AS (>10 kΩ) are possible if a
large C_AS is used and sufficient time to recharge C_AS is provided between samples. In order to achieve
accuracy specified under the worst case conditions of maximum ΔV_SAMP and minimum C_AS, R_AS must
be less than the maximum value of 10 kΩ. The maximum value of 10 kΩ for R_AS is to ensure low sampling
error in the worst case condition of maximum ΔV_SAMP and minimum C_AS.
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor
229