MC9S08GB60A Datasheet, PDF (284/302 Pages) Freescale Semiconductor, Inc – HCS08 Microcontrollers

Appendix B EB652: Migrating from the GB60 Series to the GB60A Series
improved noise immunity in the oscillator circuit. The low-power oscillator is also available for
power-sensitive applications.
This new oscillator option available on the GB60A series is selected by a new control bit in the ICG control
register 1 (ICGC1): the HGO bit. HGO is bit 7 of the ICGC1 register, formerly an unimplemented bit that
always read ‘0’. The reset value is ‘0’, which selects the low-power oscillator option—which is consistent
with the GB60 series external oscillator.
Setting HGO to ‘1’ selects the high gain external oscillator which increases the voltage swing across the
external crystal or resonator, making it more immune to external noise.
The values of the feedback and series resistors for the external oscillator will be different in most cases
between HGO=0 and HGO=1. Consult the ICG DC Electrical Specifications table in the MC9S08GB60A
data sheet for the proper values.
B.5 Internal Clock Generator: Low-Power Oscillator Maximum
Frequency
On the GB60 series, the external oscillator’s maximum frequency is 10 MHz when in FEE mode and
16 MHz when in FBE mode.
On the GB60A series, when HGO=1, the same maximum frequencies apply. However, when HGO=0, the
maximum frequency is 10 MHz in FEE and FBE modes.
B.6 Internal Clock Generator: Loss-of-Clock Disable Option
The ICG module has a clock monitor which will generate a loss-of-clock signal when either the reference
clock or the DCO clock does not meet minimum frequency requirements. This signal is used to generate
either a reset or an interrupt, depending on the settings in the ICGC2 register.
On the GB60 series, this clock monitor cannot be turned on or off by the user. The on/off status of the clock
monitor is determined by the state of the ICG module.
On the GB60A series, an option has been added to allow the user to disable the clock monitor. A new
control bit, LOCD, has been added to the ICGC1 register at bit position 1, formerly an unimplemented bit.
The reset state is ‘0’, which enables the clock monitor. Setting LOCD = 1 will disable the clock monitor
and thereby eliminate any loss-of-clock resets or interrupts.
The advantage of disabling the clock monitor is to reduce the current draw of the ICG module. Disabling
the clock monitor when running in stop3 mode with a low-range external oscillator enabled will save
approximately 9 μA of current. With LOCD=0 in this configuration, the stop3 I_DD is about 14 μA. When
LOCD=1 in this configuration, the stop I_DD is about 5 μA.
For the best combination of power conservation and system protection, Freescale Semiconductor
recommends setting the LOCD=0 whenever the MCU is in active run mode and then setting LOCD=1 just
before entering stop3 mode when OSCSTEN=1. If OSCSTEN=0, then the LOCD bit will not make a
difference in the stop3 current.
MC9S08GB60A Data Sheet, Rev. 2
284
Freescale Semiconductor