MC9S08GB60A Datasheet, PDF (272/302 Pages) Freescale Semiconductor, Inc – HCS08 Microcontrollers

Appendix A Electrical Characteristics
Table A-7. ATD Timing/Performance Characteristics¹ (continued)
No.
Characteristic
Condition
Symbol
Min
Typ
Max
Unit
9 _{Zero-scale error}⁸
1.80V < V_DDAD < 3.6V
E_ZS
—
+0.4
+1.0
LSB
10 _{Full-scale error}⁹
1.80V < V_DDAD < 3.6V
E_FS
—
+0.4
+1.0
LSB
11 _{Input leakage error} ¹⁰
1.80V < V_DDAD < 3.6V
E_IL
—
+0.05
+5
LSB
Total unadjusted
12 _error11
1.80V < V_DDAD < 3.6V
E_TU
—
+1.1
+2.5
LSB
1 _{All ACCURACY numbers are based on processor and system being in WAIT state (very little activity and no IO switching) and that}
adequate low-pass filtering is present on analog input pins (filter with 0.01 μF to 0.1 μF capacitor between analog input and V_REFL).
Failure to observe these guidelines may result in system or microcontroller noise causing accuracy errors which will vary based
on board layout and the type and magnitude of the activity.
2 _{This is the conversion time for subsequent conversions in continuous convert mode. Actual conversion time for single conversions}
or the first conversion in continuous mode is extended by one ATD clock cycle and 2 bus cycles due to starting the conversion and
setting the CCF flag. The total conversion time in Bus Cycles for a conversion is:
SC Bus Cycles = ((PRS+1)×2) × (28+1) + 2 CC Bus Cycles = ((PRS+1)×2) × (28)
3 _{RAS is the real portion of the impedance of the network driving the analog input pin. Values greater than this amount may not fully}
charge the input circuitry of the ATD resulting in accuracy error.
4 _{Analog input must be between VREFL and VREFH for valid conversion. Values greater than VREFH will convert to 0x3FF less the}
full scale error (E_FS).
5 _{The resolution is the ideal step size or 1LSB = (VREFH–VREFL)/1024}
6 _{Differential non-linearity is the difference between the current code width and the ideal code width (1LSB). The current code width}
is the difference in the transition voltages to and from the current code.
7 _{Integral non-linearity is the difference between the transition voltage to the current code and the adjusted ideal transition voltage}
for the current code. The adjusted ideal transition voltage is (Current Code–1/2)×(1/((V_REFH+E_FS)–(V_REFL+E_ZS))).
8 _{Zero-scale error is the difference between the transition to the first valid code and the ideal transition to that code. The Ideal}
transition voltage to a given code is (Code–1/2)×(1/(V_REFH–V_REFL)).
9 _{Full-scale error is the difference between the transition to the last valid code and the ideal transition to that code. The ideal}
transition voltage to a given code is (Code–1/2)×(1/(V_REFH–V_REFL)).
10 _{Input leakage error is error due to input leakage across the real portion of the impedance of the network driving the analog pin.}
Reducing the impedance of the network reduces this error.
11 _{Total unadjusted error is the difference between the transition voltage to the current code and the ideal straight-line transfer}
function. This measure of error includes inherent quantization error (1/2LSB) and circuit error (differential, integral, zero-scale, and
full-scale) error. The specified value of E_T assumes zero E_IL (no leakage or zero real source impedance).
MC9S08GB60A Data Sheet, Rev. 2
272
Freescale Semiconductor