MC9S08GB60A Datasheet, PDF (89/302 Pages) Freescale Semiconductor, Inc – HCS08 Microcontrollers

Chapter 6 Parallel Input/Output
R
W
Reset
7
PTAD7
0
6
PTAD6
5
PTAD5
4
PTAD4
3
PTAD3
2
PTAD2
0
0
0
0
0
Figure 6-9. Port A Data Register (PTAD)
1
PTAD1
0
0
PTAD0
0
Table 6-1. PTAD Field Descriptions
Field
Description
7:0
PTAD[7:0]
Port A Data Register Bits — For port A pins that are inputs, reads return the logic level on the pin. For port A
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port A pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTAD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pullups disabled.
R
W
Reset
7
PTAPE7
0
6
PTAPE6
5
PTAPE5
4
PTAPE4
3
PTAPE3
2
PTAPE2
0
0
0
0
0
Figure 6-10. Pullup Enable for Port A (PTAPE)
1
PTAPE1
0
0
PTAPE0
0
Table 6-2. PTAPE Field Descriptions
Field
Description
7:0
PTAPE[7:0]
Pullup Enable for Port A Bits — For port A pins that are inputs, these read/write control bits determine whether
internal pullup devices are enabled provided the corresponding PTADDn is 0. For port A pins that are configured
as outputs, these bits are ignored and the internal pullup devices are disabled. When any of bits 7 through 4 of
port A are enabled as KBI inputs and are configured to detect rising edges/high levels, the pullup enable bits
enable pulldown rather than pullup devices.
0 Internal pullup device disabled.
1 Internal pullup device enabled.
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor
89