MC9S08GB60A Datasheet, PDF (102/302 Pages) Freescale Semiconductor, Inc – HCS08 Microcontrollers

Chapter 6 Parallel Input/Output
R
W
Reset
7
PTGSE7
0
6
PTGSE6
5
PTGSE5
4
PTGSE4
3
PTGSE3
2
PTGSE2
1
PTGSE1
0
0
0
0
0
0
Figure 6-35. Slew Rate Control Enable for Port G (PTGSE)
0
PTGSE0
0
Table 6-27. PTGSE Field Descriptions
Field
Description
7:0
Slew Rate Control Enable for Port G Bits — For port G pins that are outputs, these read/write control bits
PTGSE[7:0] determine whether the slew rate controlled outputs are enabled. For port G pins that are configured as inputs,
these bits are ignored.
0 Slew rate control disabled.
1 Slew rate control enabled.
R
W
Reset
7
PTGDD7
0
6
PTGDD6
5
PTGDD5
4
PTGDD4
3
PTGDD3
2
PTGDD2
0
0
0
0
0
Figure 6-36. Data Direction for Port G (PTGDD)
1
PTGDD1
0
0
PTGDD0
0
Table 6-28. PTGDD Field Descriptions
Field
Description
7:0
Data Direction for Port G Bits — These read/write bits control the direction of port G pins and what is read for
PTGDD[7:0] PTGD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port G bit n and PTGD reads return the contents of PTGDn.
MC9S08GB60A Data Sheet, Rev. 2
102
Freescale Semiconductor