MC9S08GB60A Datasheet, PDF (128/302 Pages) Freescale Semiconductor, Inc – HCS08 Microcontrollers

Internal Clock Generator (S08ICGV2)
R
W
Reset
Field
7:0
FLT
7
6
5
4
3
2
1
0
FLT
1
1
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 7-17. ICG Upper Filter Register (ICGFLTL)
Table 7-11. ICGFLTL Field Descriptions
Description
Filter Value — The FLT bits indicate the current filter value, which controls the DCO frequency. The FLT bits are
read only except when the CLKS bits are programmed to self-clocked mode (CLKS = 00). In self-clocked mode,
any write to ICGFLTU updates the current 12-bit filter value. Writes to the ICGFLTU register will not affect FLT if
a previous latch sequence is not complete.
7.5.6 ICG Trim Register (ICGTRM)
R
W
POR:
Reset:
Field
7:0
TRIM
7
6
5
4
3
2
1
0
TRIM
1
0
0
0
0
0
0
0
u
u
u
u
u
u
u
u
= Unimplemented or Reserved
u = Unaffected by MCU reset
Figure 7-18. ICG Trim Register (ICGTRM)
Table 7-12. ICGTRM Field Descriptions
Description
ICG Trim Setting — The TRIM bits control the internal reference generator frequency. They allow a ± 25%
adjustment of the nominal (POR) period. The bit’s effect on period is binary weighted (i.e., bit 1 will adjust twice
as much as changing bit 0). Increasing the binary value in TRIM will increase the period and decreasing the value
will decrease the period.
MC9S08GB60A Data Sheet, Rev. 2
128
Freescale Semiconductor