MC9S08QG8_09 Datasheet, PDF (83/314 Pages) Freescale Semiconductor, Inc – HCS08 Microcontrollers

Chapter 6 Parallel Input/Output Control
6.4.2.1 Port A Internal Pullup Enable (PTAPE)
An internal pullup device can be enabled for each port pin by setting the corresponding bit in the pullup
enable register (PTAPEn). The pullup device is disabled if the pin is configured as an output by the parallel
I/O control logic or any shared peripheral function regardless of the state of the corresponding pullup
enable register bit. The pullup device is also disabled if the pin is controlled by an analog function.
7
R
0
W
6
5
4
3
2
1
0
PTAPE5
PTAPE4¹
PTAPE3
PTAPE2
PTAPE1
Reset:
0
0
0
0
0
0
0
Figure 6-4. Internal Pullup Enable for Port A Register (PTAPE)
1 _{PTAPE4 has no effect on the output-only PTA4 pin.}
0
PTAPE0
0
Table 6-3. PTAPE Register Field Descriptions
Field
Description
5:0
PTAPE[5:0]
Internal Pullup Enable for Port A Bits — Each of these control bits determines if the internal pullup device is
enabled for the associated PTA pin. For port A pins that are configured as outputs, these bits have no effect and
the internal pullup devices are disabled.
0 Internal pullup device disabled for port A bit n.
1 Internal pullup device enabled for port A bit n.
6.4.2.2 Port A Slew Rate Enable (PTASE)
Slew rate control can be enabled for each port pin by setting the corresponding bit in the slew rate control
register (PTASEn). When enabled, slew control limits the rate at which an output can transition to reduce
EMC emissions. Slew rate control has no effect on pins which are configured as inputs.
7
R
0
W
6
5
4
3
2
0
PTASE5¹
PTASE4
PTASE3
PTASE2
Reset:
0
0
1
1
1
1
Figure 6-6. Slew Rate Enable for Port A Register (PTASE)
1 _{PTASE5 has no effect on the input-only PTA5 pin.}
1
PTASE1
1
0
PTASE0
1
Table 6-4. PTASE Register Field Descriptions
Field
Description
5:0
PTASE[5:0]
Output Slew Rate Enable for Port A Bits — Each of these control bits determines if the output slew rate control
is enabled for the associated PTA pin. For port A pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port A bit n.
1 Output slew rate control enabled for port A bit n.
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
Freescale Semiconductor
81