MC9S08QG8_09 Datasheet, PDF (209/314 Pages) Freescale Semiconductor, Inc – HCS08 Microcontrollers

Serial Communications Interface (S08SCIV3)
In the case of a framing error, the receiver is inhibited from receiving any new characters until the framing
error flag is cleared. The receive shift register continues to function, but a complete character cannot
transfer to the receive data buffer if FE is still set.
14.3.3.2 Receiver Wakeup Operation
Receiver wakeup is a hardware mechanism that allows an SCI receiver to ignore the characters in a
message that is intended for a different SCI receiver. In such a system, all receivers evaluate the first
character(s) of each message, and as soon as they determine the message is intended for a different
receiver, they write logic 1 to the receiver wake up (RWU) control bit in SCIC2. When RWU = 1, it
inhibits setting of the status flags associated with the receiver, thus eliminating the software overhead for
handling the unimportant message characters. At the end of a message, or at the beginning of the next
message, all receivers automatically force RWU to 0 so all receivers wake up in time to look at the first
character(s) of the next message.
14.3.3.2.1 Idle-Line Wakeup
When WAKE = 0, the receiver is configured for idle-line wakeup. In this mode, RWU is cleared
automatically when the receiver detects a full character time of the idle-line level. The M control bit selects
8-bit or 9-bit data mode that determines how many bit times of idle are needed to constitute a full character
time (10 or 11 bit times because of the start and stop bits).
When the RWU bit is set, the idle character that wakes a receiver does not set the receiver idle bit, IDLE,
or the receive data register full flag, RDRF. It therefore will not generate an interrupt when this idle
character occurs. The receiver will wake up and wait for the next data transmission which will set RDRF
and generate an interrupt if enabled.
The idle-line type (ILT) control bit selects one of two ways to detect an idle line. When ILT = 0, the idle
bit counter starts after the start bit so the stop bit and any logic 1s at the end of a character count toward
the full character time of idle. When ILT = 1, the idle bit counter does not start until after a stop bit time,
so the idle detection is not affected by the data in the last character of the previous message.
14.3.3.2.2 Address-Mark Wakeup
When WAKE = 1, the receiver is configured for address-mark wakeup. In this mode, RWU is cleared
automatically when the receiver detects a logic 1 in the most significant bit of a received character (eighth
bit in M = 0 mode and ninth bit in M = 1 mode).
Address-mark wakeup allows messages to contain idle characters but requires that the MSB be reserved
for use in address frames. The logic 1 MSB of an address frame clears the receivers RWU bit before the
stop bit is received and sets the RDRF flag.
14.3.4 Interrupts and Status Flags
The SCI system has three separate interrupt vectors to reduce the amount of software needed to isolate the
cause of the interrupt. One interrupt vector is associated with the transmitter for TDRE and TC events.
Another interrupt vector is associated with the receiver for RDRF and IDLE events, and a third vector is
used for OR, NF, FE, and PF error conditions. Each of these eight interrupt sources can be separately
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
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