MC9S08QG8_09 Datasheet, PDF (111/314 Pages) Freescale Semiconductor, Inc – HCS08 Microcontrollers

Analog Comparator (S08ACMPV2)
8.1.3 Features
The ACMP has the following features:
• Full rail-to-rail supply operation.
• Less than 40 mV of input offset.
• Less than 15 mV of hysteresis.
• Selectable interrupt on rising edge, falling edge, or either rising or falling edges of comparator
output.
• Option to compare to fixed internal bandgap reference voltage.
• Option to allow comparator output to be visible on a pin, ACMPO.
8.1.4 Modes of Operation
This section defines the ACMP operation in wait, stop, and background debug modes.
8.1.4.1 ACMP in Wait Mode
The ACMP continues to run in wait mode if enabled before executing the WAIT instruction. Therefore,
the ACMP can be used to bring the MCU out of wait mode if the ACMP interrupt, ACIE, is enabled. For
lowest possible current consumption, the ACMP should be disabled by software if not required as an
interrupt source during wait mode.
8.1.4.2 ACMP in Stop Modes
The ACMP is disabled in all stop modes, regardless of the settings before executing the STOP instruction.
Therefore, the ACMP cannot be used as a wake up source from stop modes.
During either stop1 or stop2 mode, the ACMP module will be fully powered down. Upon wake-up from
stop1 or stop2 mode, the ACMP module will be in the reset state.
During stop3 mode, clocks to the ACMP module are halted. No registers are affected. In addition, the
ACMP comparator circuit will enter a low power state. No compare operation will occur while in stop3.
If stop3 is exited with a reset, the ACMP will be put into its reset state. If stop3 is exited with an interrupt,
the ACMP continues from the state it was in when stop3 was entered.
8.1.4.3 ACMP in Active Background Mode
When the microcontroller is in active background mode, the ACMP will continue to operate normally.
8.1.5 Block Diagram
The block diagram for the analog comparator module is shown Figure 8-2.
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
Freescale Semiconductor
109