MC9S08QG8_09 Datasheet, PDF (73/314 Pages) Freescale Semiconductor, Inc – HCS08 Microcontrollers

Chapter 5 Resets, Interrupts, and General System Control
5.8.5 System Options Register 2 (SOPT2)
This high page register contains bits to configure MCU specific features on the MC9S08QG8/4 devices.
7
6
5
4
3
2
R
0
0
0
0
0
COPCLKS¹
W
Reset:
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 5-6. System Options Register 2 (SOPT2)
1 _{This bit can be written only one time after reset. Additional writes are ignored.}
Table 5-7. SOPT2 Register Field Descriptions
1
IICPS
0
0
ACIC
0
Field
Description
7
COP Watchdog Clock Select — This write-once bit selects the clock source of the COP watchdog.
COPCLKS 0 Internal 1-kHz clock is source to COP.
1 Bus clock is source to COP.
1
IICPS
IIC Pin Select— This bit selects the location of the SDA and SCL pins of the IIC module.
0 SDA on PTA2, SCL on PTA3.
1 SDA on PTB6, SCL on PTB7.
0
ACIC
Analog Comparator to Input Capture Enable— This bit connects the output of ACMP to TPM input channel 0.
0 ACMP output not connected to TPM input channel 0.
1 ACMP output connected to TPM input channel 0.
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
Freescale Semiconductor
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