MC9S08QG8_09 Datasheet, PDF (150/314 Pages) Freescale Semiconductor, Inc – HCS08 Microcontrollers

Internal Clock Source (S08ICSV1)
10.3.2 ICS Control Register 2 (ICSC2)
R
W
Reset:
7
6
BDIV
5
RANGE
4
HGO
3
2
1
0
LP
EREFS ERCLKEN EREFSTEN
0
1
0
0
0
0
0
0
Figure 10-4. ICS Control Register 2 (ICSC2)
Table 10-2. ICS Control Register 2 Field Descriptions
Field
Description
7:6
BDIV
Bus Frequency Divider — Selects the amount to divide down the clock source selected by the CLKS bits. This
controls the bus frequency.
00 Encoding 0 — Divides selected clock by 1
01 Encoding 1 — Divides selected clock by 2 (reset default)
10 Encoding 2 — Divides selected clock by 4
11 Encoding 3 — Divides selected clock by 8
5
RANGE
Frequency Range Select — Selects the frequency range for the external oscillator.
1 High frequency range selected for the external oscillator
0 Low frequency range selected for the external oscillator
4
HGO
High Gain Oscillator Select — The HGO bit controls the external oscillator mode of operation.
1 Configure external oscillator for high gain operation
0 Configure external oscillator for low power operation
3
Low Power Select — The LP bit controls whether the FLL is disabled in FLL bypassed modes.
LP
1 FLL is disabled in bypass modes unless BDM is active
0 FLL is not disabled in bypass mode
2
EREFS
External Reference Select — The EREFS bit selects the source for the external reference clock.
1 Oscillator requested
0 External Clock Source requested
1
External Reference Enable — The ERCLKEN bit enables the external reference clock for use as ICSERCLK.
ERCLKEN 1 ICSERCLK active
0 ICSERCLK inactive
0
External Reference Stop Enable — The EREFSTEN bit controls whether or not the external reference clock
EREFSTEN remains enabled when the ICS enters stop mode.
1 External reference clock stays enabled in stop if ERCLKEN is set or if ICS is in FEE, FBE, or FBELP mode
before entering stop
0 External reference clock is disabled in stop
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
148
Freescale Semiconductor