MC9S08QG8_09 Datasheet, PDF (77/314 Pages) Freescale Semiconductor, Inc – HCS08 Microcontrollers

Chapter 5 Resets, Interrupts, and General System Control
5.8.9 System Power Management Status and Control 2 Register
(SPMSC2)
This high page register contains status and control bits to configure the stop mode behavior of the MCU.
See Section 3.6, “Stop Modes,” for more information on stop modes.
7
6
5
4
3
2
1
R
0
0
0
PDF
PPDF
0
PDC¹
W
PPDACK
Reset:
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 5-11. System Power Management Status and Control 2 Register (SPMSC2)
1 _{This bit can be written only one time after reset. Additional writes are ignored.}
Table 5-13. SPMSC2 Register Field Descriptions
0
PPDC¹
0
Field
Description
4
PDF
3
PPDF
2
PPDACK
1
PDC
0
PPDC
Power Down Flag — This read-only status bit indicates the MCU has recovered from stop1 mode.
0 MCU has not recovered from stop1 mode.
1 MCU recovered from stop1 mode.
Partial Power Down Flag — This read-only status bit indicates that the MCU has recovered from stop2 mode.
0 MCU has not recovered from stop2 mode.
1 MCU recovered from stop2 mode.
Partial Power Down Acknowledge — Writing a 1 to PPDACK clears the PPDF and the PDF bits.
Power Down Control — The PDC bit controls entry into the power down (stop2 and stop1) modes.
0 Power down modes are disabled.
1 Power down modes are enabled.
Partial Power Down Control — The PPDC bit controls which power down mode is selected.
0 Stop1 full power down mode enabled if PDC set.
1 Stop2 partial power down mode enabled if PDC set.
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
Freescale Semiconductor
75