MC9S08QG8_09 Datasheet, PDF (70/314 Pages) Freescale Semiconductor, Inc – HCS08 Microcontrollers

Chapter 5 Resets, Interrupts, and General System Control
5.8.2 System Reset Status Register (SRS)
This high page register includes read-only status flags to indicate the source of the most recent reset. When
a debug host forces reset by writing 1 to BDFR in the SBDFR register, all of the status bits in SRS will be
cleared. Writing any value to this register address clears the COP watchdog timer without affecting the
contents of this register. The reset state of these bits depends on what caused the MCU to reset.
7
6
5
4
3
2
1
0
R POR
PIN
COP
ILOP
ILAD
0
LVD
0
W
Writing any value to SRS address clears COP watchdog timer.
POR:
1
0
0
0
0
0
1
0
LVD:
u⁽¹⁾
0
0
0
0
0
1
0
Any other
reset:
0
Note ⁽²⁾
Note ⁽²⁾
Note ⁽²⁾
Note ⁽²⁾
0
0
0
Figure 5-3. System Reset Status (SRS)
1 _{u = unaffected}
2 _{Any of these reset sources that are active at the time of reset entry will cause the corresponding bit(s) to be set; bits}
corresponding to sources that are not active at the time of reset entry will be cleared.
Table 5-4. SRS Register Field Descriptions
Field
7
POR
6
PIN
5
COP
4
ILOP
3
ILAD
1
LVD
Description
Power-On Reset — Reset was caused by the power-on detection logic. Because the internal supply voltage was
ramping up at the time, the low-voltage reset (LVD) status bit is also set to indicate that the reset occurred while
the internal supply was below the LVD threshold.
0 Reset not caused by POR.
1 POR caused reset.
External Reset Pin — Reset was caused by an active-low level on the external reset pin.
0 Reset not caused by external reset pin.
1 Reset came from external reset pin.
Computer Operating Properly (COP) Watchdog — Reset was caused by the COP watchdog timer timing out.
This reset source can be blocked by COPE = 0.
0 Reset not caused by COP timeout.
1 Reset caused by COP timeout.
Illegal Opcode — Reset was caused by an attempt to execute an unimplemented or illegal opcode. The STOP
instruction is considered illegal if stop is disabled by STOPE = 0 in the SOPT1 register. The BGND instruction is
considered illegal if active background mode is disabled by ENBDM = 0 in the BDCSC register.
0 Reset not caused by an illegal opcode.
1 Reset caused by an illegal opcode.
Illegal Address — Reset was caused by an attempt to access either data or an instruction at an unimplemented
memory address.
0 Reset not caused by an illegal address
1 Reset caused by an illegal address
Low Voltage Detect — If the LVDRE bit is set and the supply drops below the LVD trip voltage, an LVD reset will
occur. This bit is also set by POR.
0 Reset not caused by LVD trip or POR.
1 Reset caused by LVD trip or POR.
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
68
Freescale Semiconductor