MC9S08QG8_09 Datasheet, PDF (199/314 Pages) Freescale Semiconductor, Inc – HCS08 Microcontrollers

Serial Communications Interface (S08SCIV3)
14.2 Register Definition
The SCI has eight 8-bit registers to control baud rate, select SCI options, report SCI status, and for
transmit/receive data.
Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address
assignments for all SCI registers. This section refers to registers and control bits only by their names. A
Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
14.2.1 SCI Baud Rate Registers (SCIBDH, SCIBDL)
This pair of registers controls the prescale divisor for SCI baud rate generation. To update the 13-bit baud
rate setting [SBR12:SBR0], first write to SCIBDH to buffer the high half of the new value and then write
to SCIBDL. The working value in SCIBDH does not change until SCIBDL is written.
SCIBDL is reset to a non-zero value, so after reset the baud rate generator remains disabled until the first
time the receiver or transmitter is enabled (RE or TE bits in SCIC2 are written to 1).
7
6
5
4
3
2
R
0
0
0
SBR12
SBR11
SBR10
W
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 14-5. SCI Baud Rate Register (SCIBDH)
1
SBR9
0
0
SBR8
0
Table 14-1. SCIBDH Register Field Descriptions
Field
Description
4:0
Baud Rate Modulo Divisor — These 13 bits are referred to collectively as BR, and they set the modulo divide
SBR[12:8] rate for the SCI baud rate generator. When BR = 0, the SCI baud rate generator is disabled to reduce supply
current. When BR = 1 to 8191, the SCI baud rate = BUSCLK/(16×BR). See also BR bits in Table 14-2.
R
W
Reset
7
SBR7
0
6
SBR6
5
SBR5
4
SBR4
3
SBR3
2
SBR2
0
0
0
0
1
Figure 14-6. SCI Baud Rate Register (SCIBDL)
1
SBR1
0
0
SBR0
0
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
Freescale Semiconductor
197