K10P81M100SF2 Datasheet, PDF (51/60 Pages) Freescale Semiconductor, Inc – K10 Sub-Family Data Sheet

Peripheral operating requirements and behaviors
I2S_MCLK (output)
S1
S2
S2
S3
I2S_BCLK (output)
S4
S4
S5
S6
I2S_FS (output)
S9
S10
I2S_FS (input)
S7
I2S_TXD
I2S_RXD
Num
S11
S12
S13
S14
S15
S16
S17
S18
S7
S8
S8
S9
S10
ry _{Figure 22. I2S timing — master mode}
a _{Table 40. I}2_{S alave mode timing}
Description
in ^{Operating voltage}
Min.
2.7
Max.
3.6
Unit
V
I2S_BCLK cycle time (input)
I2S_BCLK pulse width high/low (input)
lim ^{I2S_FS input setup before I2S_BCLK}
I2S_FS input hold after I2S_BCLK
I2S_BCLK to I2S_TXD/I2S_FS output valid
I2S_BCLK to I2S_TXD/I2S_FS output invalid
e _{I2S_RXD setup before I2S_BCLK}
Pr ^{I2S_RXD hold after I2S_BCLK}
8 x t_SYS
45%
10
3
—
0
10
2
—
55%
—
—
20
—
—
—
ns
MCLK period
ns
ns
ns
ns
ns
ns
S11
S12
I2S_BCLK (input)
S12
I2S_FS (output)
S15
S13
S16
S14
I2S_FS (input)
S15
S15
S16
S16
I2S_TXD
I2S_RXD
S17
S18
Figure 23. I²S timing — slave modes
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
Preliminary
51