K10P81M100SF2 Datasheet, PDF (48/60 Pages) Freescale Semiconductor, Inc – K10 Sub-Family Data Sheet

Peripheral operating requirements and behaviors
Table 36. Master Mode DSPI Timing (High-speed mode) (continued)
Num
Description
Min.
Max.
Unit
DS3
DSPI_PCSn to DSPI_SCK output valid
(t_SCK/2) − 2
—
ns
DS4
DSPI_SCK to DSPI_PCSn output hold
(t_SCK/2) − 2
—
ns
DS5
DSPI_SCK to DSPI_SOUT valid
—
8.5
ns
DS6
DSPI_SCK to DSPI_SOUT invalid
−2
—
ns
DS7
DSPI_SIN to DSPI_SCK input setup
TBD
—
ns
DS8
DSPI_SCK to DSPI_SIN input hold
0
—
ns
DSPI_PCSn
DSPI_SCK
(CPOL=0)
DSPI_SIN
DSPI_SOUT
DS3
DS7
DS8
First data
DS2
DS5
First data
y _DS1
DS4
ar Data
Last data
DS6
in ^Data
Last data
Num
DS9
DS10
DS11
Figure 19. DSPI Classic SPI Timing — Master Mode
lim ^{Table 37. Slave Mode DSPI Timing (High-speed mode)}
Operating voltage
Description
Frequency of operation
e _{DSPI_SCK input cycle time}
r _{DSPI_SCK input high/low time}
P ^{DSPI_SCK to DSPI_SOUT valid}
Min.
2.7
4 x t_BCLK
(t_SCK/2) − 2
—
Max.
3.6
12.5
—
(t_SCK/2 + 2
TBD
Unit
V
MHz
ns
ns
ns
DS12
DSPI_SCK to DSPI_SOUT invalid
0
—
ns
DS13
DSPI_SIN to DSPI_SCK input setup
2
—
ns
DS14
DSPI_SCK to DSIP_SIN input hold
7
—
ns
DS15
DSPI_SS active to DSPI_SOUT driven
—
14
ns
DS16
DSPI_SS inactive to DSPI_SOUT not driven
—
14
ns
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
48
Preliminary
Freescale Semiconductor, Inc.