K10P81M100SF2 Datasheet, PDF (50/60 Pages) Freescale Semiconductor, Inc – K10 Sub-Family Data Sheet

Peripheral operating requirements and behaviors
SDHC_CLK
SD3
SD2
SD1
SD6
Output SDHC_CMD
Output SDHC_DAT[3:0]
SD7
SD8
Input SDHC_CMD
ry ^{Input SDHC_DAT[3:0]}
Figure 21. SDHC timing
a _{6.8.4 I2S Switching Specifications}
in This section provides the AC timings for the I²S in master (clocks driven) and slave
modes (clocks input). All timings are given for non-inverted serial clock polarity
(TCR[TSCKP] = 0, RCR[RSCKP] = 0) and a non-inverted frame sync (TCR[TFSI] = 0,
lim ^{RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all}
the timings remain valid by inverting the clock signal (I2S_BCLK) and/or the frame sync
(I2S_FS) shown in the figures below.
Table 39. _I²_{S master mode timing}
e _Num
Pr ^S1
Description
Operating voltage
I2S_MCLK cycle time
Min.
2.7
2 x t_SYS
Max.
3.6
Unit
V
ns
S2
I2S_MCLK pulse width high/low
45%
55%
MCLK period
S3
I2S_BCLK cycle time
5 x t_SYS
—
ns
S4
I2S_BCLK pulse width high/low
45%
55%
BCLK period
S5
I2S_BCLK to I2S_FS output valid
—
15
ns
S6
I2S_BCLK to I2S_FS output invalid
-2.5
—
ns
S7
I2S_BCLK to I2S_TXD valid
—
15
ns
S8
I2S_BCLK to I2S_TXD invalid
-3
—
ns
S9
I2S_RXD/I2S_FS input setup before I2S_BCLK
20
—
ns
S10
I2S_RXD/I2S_FS input hold after I2S_BCLK
0
—
ns
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
50
Preliminary
Freescale Semiconductor, Inc.