K10P81M100SF2 Datasheet, PDF (47/60 Pages) Freescale Semiconductor, Inc – K10 Sub-Family Data Sheet

Peripheral operating requirements and behaviors
Table 35. Slave Mode DSPI Timing (Low-speed Mode) (continued)
Num
Description
Min.
Max.
Unit
DS9
DSPI_SCK input cycle time
8 x t_BCLK
—
ns
DS10
DSPI_SCK input high/low time
(t_SCK/2) - 4
(t_SCK/2) + 4
ns
DS11
DSPI_SCK to DSPI_SOUT valid
—
20
ns
DS12
DSPI_SCK to DSPI_SOUT invalid
0
—
ns
DS13
DSPI_SIN to DSPI_SCK input setup
5
—
ns
DS14
DSPI_SCK to DSIP_SIN input hold
15
—
ns
DS15
DS16
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
DSPI_SS
DSPI_SCK
(CPOL=0)
DS15
DS10
DS12
—
15
—
15
ry _DS9
ina^DS11
DS16
ns
ns
DSPI_SOUT
DSPI_SIN
DS13
First data
DS14
First data
Data
Data
Last data
Last data
lim _{Figure 18. DSPI Classic SPI Timing — Slave Mode}
re _{6.8.2 DSPI Switching Specifications (High-speed mode)}
P ^{The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with}
master and slave operations. Many of the transfer attributes are programmable. The tables
below provide DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 36. Master Mode DSPI Timing (High-speed mode)
Num
DS1
DS2
Operating voltage
Description
Frequency of operation
DSPI_SCK output cycle time
DSPI_SCK output high/low time
Min.
2.7
—
2 x t_BCLK
(t_SCK/2) − 2
Max.
3.6
25
—
(t_SCK/2) + 2
Unit
V
MHz
ns
ns
Table continues on the next page...
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
Preliminary
47