K10P81M100SF2 Datasheet, PDF (40/60 Pages) Freescale Semiconductor, Inc – K10 Sub-Family Data Sheet

Peripheral operating requirements and behaviors
Table 26. 16-bit ADC with PGA characteristics (continued)
Symbol
E_IL
V_PP,DIFF
SNR
THD
SFDR
ENOB
SINAD
Description
Conditions
Min.
Typ.¹
Max.
Unit
Notes
Input leakage er‐ All modes
ror
I_In × R_AS
mV
I_In = leakage
current
(refer to the
MCU's voltage
and current op‐
erating ratings)
Maximum differ‐
ential input signal
swing
Signal-to-noise
ratio
Total harmonic
distortion
Spurious free dy‐
namic range
Effective number
of bits
Signal-to-noise
plus distortion ra‐
tio
[(V_REFPGA × 2.33) - 0.2] / (2 ×
V
4
Gain)
• Gain=1
• Gain=64
• Gain=1
• Gain=64
• Gain=1
• Gain=64
• Gain=1, Average=4
• Gain=1, Average=8
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
8.3
—
57.7
—
y _87.3
—
r ^85.3
—
92.42
—
a 92.54
—
12.3
—
in^12.7
—
dB
Average=32
dB
dB
Average=32,
dB
f_in=100Hz
dB
Average=32,
dB
f_in=100Hz
bits
bits
• Gain=64, Average=4
• Gain=64, Average=8
• Gain=1, Average=32
lim ^{• Gain=2, Average=32}
• Gain=4, Average=32
• Gain=8, Average=32
• Gain=16, Average=32
e _{• Gain=32, Average=32}
r• Gain=64, Average=32
P^{See ENOB}
TBD
8.4
—
TBD
8.7
—
TBD
13.4
—
TBD
13.1
—
TBD
12.6
—
TBD
11.8
—
TBD
11.1
—
TBD
10.2
—
TBD
9.3
—
6.02 × ENOB + 1.76
bits
bits
bits
bits
bits
bits
bits
bits
bits
dB
1. Typical values assume V_DDA =3.0V, Temp=25°C, f_ADCK=6MHz unless otherwise stated.
2. _{Gain = 2}^PGAGx
3. When the PGA gain is changed, it takes some time to settle the output for the ADC to work properly. During a gain
switching, a few ADC outputs should be discarded (minimum two data samples, may be more depending on ADC
sampling rate and time of the switching).
4. Limit the input signal swing so that the PGA does not saturate during operation. Input signal swing is dependent on the
PGA reference voltage and gain setting.
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
40
Preliminary
Freescale Semiconductor, Inc.