K10P81M100SF2 Datasheet, PDF (39/60 Pages) Freescale Semiconductor, Inc – K10 Sub-Family Data Sheet

Peripheral operating requirements and behaviors
4. The analog source resistance (R_AS), external to MCU, should be kept as minimum as possible. Increased R_AS causes drop
in PGA gain without affecting other performances. This is not dependent on ADC clock frequency.
5. The minimum sampling time is dependent on input signal frequency and ADC mode of operation. A minimum of 1.25µs
time should be allowed for F_in=4 kHz at 16-bit differential mode. Recommended ADC setting is: ADLSMP=1, ADLSTS=2 at
8 MHz ADC clock. The ADLSTS bits can be adjusted for different ADC clock frequency
6.6.1.4 16-bit ADC with PGA characteristics
Table 26. 16-bit ADC with PGA characteristics
Symbol
I_{DDA_PGA}
I_LKG
G
G_A
BW
PSRR
CMRR
V_OFS
Description
Conditions
Min.
Typ.¹
Max.
Unit
Notes
Supply current
Leakage current
Gain²
PGA disabled
• PGAG=0
• PGAG=1
• PGAG=2
• PGAG=3
• PGAG=4
• PGAG=5
• PGAG=6
TBD
—
TBD
TBD
TBD
TBD
TBD
TBD
TBD
590
TBD
μA
<1
TBD
μA
y ¹
TBD
dB
R_AS < 100Ω
2
TBD
dB
r _3.9
TBD
dB
TBD
TBD
dB
a_TBD
TBD
dB
29.9
TBD
dB
in^TBD
TBD
dB
Gain error
Input signal band‐
width
• 16-bit modes
• < 16-bit modes
lim ^{Power supply re‐ Gain=1}
jection ration
e _{Common mode}
Pr ^{rejection ratio}
• Gain=1
• Gain=64
—
—
—
TBD
—
—
—
TBD
TBD
TBD
TBD
TBD
±0.5
4
40
—
—
—
dB
R_AS < 100Ω
kHz
kHz
dB
V_DDA= 3V
±100mV,
f_VDDA= 50Hz,
60Hz
dB
V_CM=
dB
500mVpp,
f_VCM= 50Hz,
100Hz
Input offset volt‐
—
0.2
TBD
mV
Gain=1, ADC
age
Averaging=32
T_GSW
Gain switching
settling time
—
TBD
10
µs
3
dG/dT
Gain drift over
temperature
• Gain=1
• Gain=64
—
TBD
TBD ppm/°C 0 to 50°C
—
TBD
TBD ppm/°C
dV_OFS/dT Offset drift over
temperature
Gain=1
—
TBD
TBD ppm/°C 0 to 50°C, ADC
Averaging=32
dG/dV_DDA Gain drift over
supply voltage
• Gain=1
• Gain=64
—
TBD
TBD
%/V V_DDA from 1.71
—
TBD
TBD
%/V
to 3.6V
Table continues on the next page...
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
Preliminary
39