K10P81M100SF2 Datasheet, PDF (46/60 Pages) Freescale Semiconductor, Inc – K10 Sub-Family Data Sheet

Peripheral operating requirements and behaviors
6.8.1 DSPI Switching Specifications for Low-speed Operation
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provides DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 34. Master Mode DSPI Timing (Low-speed mode)
Num
ry _DS1
DS2
a _DS3
DS4
in ^DS5
DS6
DS7
lim ^DS8
Operating voltage
Description
Frequency of operation
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn to DSPI_SCK output valid
DSPI_SCK to DSPI_PCSn output hold
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
Min.
1.71
—
4 x t_BCLK
(t_SCK/2) - 4
(t_SCK/2) - 4
(t_SCK/2) - 4
—
-2
15
0
Max.
3.6
12.5
—
(t_SCK/2) + 4
—
—
10
—
—
—
Unit
V
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
e _{DSPI_PCSn}
r _{DSPI_SCK}
P _(CPOL=0)
DS3
DS2
DS7
DS8
DS1
DS4
DSPI_SIN
First data
Data
DS5
Last data
DS6
DSPI_SOUT
First data
Data
Last data
Figure 17. DSPI Classic SPI Timing — Master Mode
Table 35. Slave Mode DSPI Timing (Low-speed Mode)
Num
Description
Operating voltage
Frequency of operation
Min.
1.71
—
Max.
3.6
6.25
Unit
V
MHz
Table continues on the next page...
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
46
Preliminary
Freescale Semiconductor, Inc.