K10P81M100SF2 Datasheet, PDF (24/60 Pages) Freescale Semiconductor, Inc – K10 Sub-Family Data Sheet

Peripheral operating requirements and behaviors
Table 12. MCG specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
t_irefstf Internal reference startup time (fast clock)
—
TBD
TBD
µs
f_{loc_low} Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
—
f_{ints_t}
—
kHz
f_{loc_high} Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
—
f_{ints_t}
—
kHz
FLL
f_{dco_t} DCO output fre‐
Low range (DRS=00)
20
quency range —
user trimmed
640 × f_{ints_t}
and DMX32=0
Mid range (DRS=01)
40
y ^{1280 × fints_t}
Mid-high range (DRS=10
60
r _{192)0 × fints_t}
a ^{High range (DRS=11)}
80
2560 × f_{ints_t}
in ^{fdco_t_DMX3 DCO output fre‐}
Low range (DRS=00)
—
2
quency range —
reference =
732 × f_{ints_t}
32,768Hz and
Mid range (DRS=01)
—
DMX32=1
1464 × f_{ints_t}
lim ^{Mid-high range (DRS=10)}
—
2197 × f_{ints_t}
High range (DRS=11)
—
2929 × f_{ints_t}
e _{Jcyc_fll FLL period jitter}
—
r _{Jacc_fll FLL accumulated jitter of DCO output over a 1µs}
—
P ^{time window}
20.97
41.94
62.91
83.89
23.99
47.97
71.99
95.98
TBD
TBD
25
50
75
100
—
—
—
—
TBD
TBD
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ps
ps
t_{fll_acquire} FLL target frequency acquisition time
—
—
1
ms
PLL
f_vco
VCO operating frequency
48.0
—
100
MHz
f_{pll_ref} PLL reference frequency range
2.0
—
4.0
MHz
J_{cyc_pll} PLL period jitter
—
400
—
ps
J_{acc_pll} PLL accumulated jitter over 1µs window
—
TBD
—
ps
D_lock Lock entry frequency tolerance
± 1.49
—
± 2.98
%
D_unl Lock exit frequency tolerance
± 4.47
—
± 5.97
%
t_{pll_lock} Lock detector detection time
—
—
0.15 +
ms
1075(1/
f_{pll_ref})
1. The resulting system clock frequencies should not exceed their maximum specified values.
Notes
1, 2
3
4
5
6, 7
6,7
8
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
24
Preliminary
Freescale Semiconductor, Inc.