K10P81M100SF2 Datasheet, PDF (21/60 Pages) Freescale Semiconductor, Inc – K10 Sub-Family Data Sheet

Symbol
J3
Peripheral operating requirements and behaviors
Table 11. JTAG electricals (continued)
Description
TCLK clock pulse width
• JTAG and CJTAG
• Serial Wire Debug
Min.
Max.
Unit
ns
20
—
10
—
J4
TCLK rise and fall times
—
3
ns
J5
Boundary scan input data setup time to TCLK rise
20
—
ns
J6
Boundary scan input data hold time after TCLK rise
0
—
ns
J7
TCLK low to boundary scan output data valid
J8
TCLK low to boundary scan output high-Z
J9
TMS, TDI input data setup time to TCLK rise
J10
TMS, TDI input data hold time after TCLK rise
J11
TCLK low to TDO data valid
J12
TCLK low to TDO high-Z
J13
TRST assert time
J14
TRST setup time (negation) to TCLK high
—
30
—
30
16
—
y ₁
—
r_—
4
—
4
a₁₀₀
—
in⁸
—
ns
ns
ns
ns
ns
ns
ns
ns
TCLK (input)
J2
J3
J3
lim J4
J4
Pre^{Figure 5. Test clock input timing}
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
Preliminary
21