K10P81M100SF2 Datasheet, PDF (15/60 Pages) Freescale Semiconductor, Inc – K10 Sub-Family Data Sheet

5.1.5 Power consumption operating behaviors
Table 5. Power consumption operating behaviors
General
Symbol Description
Min.
Typ.
Max.
Unit
I_{DD_RUN} Run mode current — all peripheral clocks disa‐
bled, code executing from flash
• @ 1.8V
• @ 3.0V
—
40
TBD
mA
—
42
TBD
mA
I_{DD_RUN}
I_{DD_RUN_M}
AX
I_{DD_WAIT}
I_{DD_STOP}
I_{DD_VLPR}
I_{DD_VLPR}
I_{DD_VLPW}
I_{DD_VLPS}
I_{DD_LLS}
I_{DD_VLLS3}
I_{DD_VLLS2}
Run mode current — all peripheral clocks ena‐
bled, code executing from flash
• @ 1.8V
—
• @ 3.0V
—
y Run mode current — all peripheral clocks ena‐
bled and peripherals active, code executing from
r flash
• @ 1.8V
—
a ^{• @ 3.0V}
—
Wait mode current at 3.0 V — all peripheral
—
in ^{clocks disabled}
Stop mode current at 3.0 V
—
Very-low-power run mode current at 3.0 V — all
—
peripheral clocks disabled
lim ^{Very-low-power run mode current at 3.0 V — all}
—
peripheral clocks enabled
Very-low-power wait mode current at 3.0 V
—
Very-low-power stop mode current at 3.0 V
—
e _{Low leakage stop mode current at 3.0 V}
—
r ^{Very low-leakage stop mode 3 current at 3.0 V}
P ^{• 128KB RAM devices}
—
55
TBD
mA
56
TBD
mA
85
TBD
mA
85
TBD
mA
15
TBD
mA
1.4
TBD
mA
1.25
TBD
mA
TBD
TBD
mA
1.05
TBD
mA
30
TBD
μA
12
TBD
μA
8
TBD
μA
Very low-leakage stop mode 2 current at 3.0 V
—
4
TBD
μA
I_{DD_VLLS1} Very low-leakage stop mode 1 current at 3.0 V
—
2
TBD
μA
I_{DD_VBAT} Average current when CPU is not accessing
RTC registers at 3.0 V
—
550
TBD
nA
Notes
1
2
3
4
5
6
7
1. 100MHz core and system clock, 50MHz bus and FlexBus clock, and 25MHz flash clock . MCG configured for FEI mode.
All peripheral clocks disabled.
2. 100MHz core and system clock, 50MHz bus and FlexBus clock, and 25MHz flash clock. MCG configured for FEI mode. All
peripheral clocks enabled, but peripherals are not in active operation.
3. 100MHz core and system clock, 50MHz bus and FlexBus clock, and 25MHz flash clock. MCG configured for FEI mode. All
peripheral clocks enabled, and peripherals are in active operation.
4. 25MHz core and system clock, 25MHz bus clock, and 12.5MHz FlexBus and flash clock. MCG configured for FEI mode.
5. 2 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for fast IRCLK mode. All peripheral
clocks disabled. Code executing from flash.
6. 2 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for fast IRCLK mode. All peripheral
clocks enabled but peripherals are not in active operation. Code executing from flash.
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
Preliminary
15