MC33596_10 Datasheet, PDF (43/70 Pages) Freescale Semiconductor, Inc – PLL Tuned UHF Receiver for Data Transfer Applications

00h CONFIG1-A
91 h
Bit 7
Bit 6
Bit Name LOF1 LOF0
Reset
1
0
Value
R/W
R/W
0=
304–434 304–315
1=
315–916 434–916
01h CONFIG2-A
10 h
Bit 7
Bit 6
Bit Name DSREF FRM
Reset
0
0
Value
R/W
R/W
0=
Fixed Friendly
1=
Adaptive Direct
02h CONFIG3-A
30 h
Bit 7
Bit 6
Bit Name AFF1 AFF0
Reset
0
0
Value
R/W
R/W
0=
0.5–1 0.5–2
kHz
kHz
1=
2–4 kHz 1–4 kHz
03h COMMAND-A 9 h
Bit 7
Bit 6
Bit Name AFFC IFLA
Reset
0
0
Value
R/W
R/W
0=
AFFx
No
OFF
1=
AFFx ON –20 dB
04h F1-A
48 h
Bit 7
Bit 6
Bit Name —
—
Reset
0
1
Value
R/W
R/W
05h F2-A
0h
Bit 7
Bit 6
Bit Name F7
F6
Reset
0
0
Value
R/W
R/W
Bit 5
CF1
0
Bit 4
CF0
1
Bit 3
RESET
0
Bit 2
SL
0
R/W
R/W
R/W
R/W
315–434 314
No
T/R
868
434–868 Yes
R/T
Bit 5
MODU
0
Bit 4
DR1
1
Bit 3
DR0
0
Bit 2
TRXE
0
R/W
OOK
FSK
R/W
2.4–4.8
9.6–19.2
R/W
2.4–9.6
4.8–19.2
R/W
Standby
Enable
Bit 5
OLS
1
Bit 4
LVDS
1
R
RAS
RR
RAS
Unlocked Low V
Bit 3
ILA1
0
Bit 2
ILA0
0
R/W
0–8 dB
R/W
0–14 dB
14–24 dB 8–24 dB
Bit 5
—
0
R/W
RX
TX
Bit 4
RSSIE
0
R/W
No
Yes
Bit 3
EDD
1
Bit 2
RAGC
0
R/W
R/W
Slow dec. No
Fast dec. Yes
Bit 5
—
0
R/W
Bit 4
—
0
R/W
Bit 3
F11
1
R/W
Bit 2
F10
0
R/W
Bit 5
F5
0
Bit 4
F4
0
Bit 3
F3
0
R/W
R/W
R/W
Bank A Registers
Bit 2
F1
0
R/W
Bit 1
LVDE
0
R/W
No
Yes
Bit 0
CLKE
1
R/W
No
Yes
Bit 1
DME
0
R/W
No
Yes
Bit 0
SOE
0
R/W
No
Yes
Bit 1
—
0
Bit 0
—
0
R/W
0–8 dB
R/W
0–14 dB
14–24 dB 8–24 dB
Bit 1
FAGC
0
R/W
No
Yes
Bit 0
BANKS
1
R
B Bank
A Bank
Bit 1
F9
0
R/W
Bit 0
F8
0
R/W
Bit 1
F1
0
R/W
Bit 0
F0
0
R/W
0Dh CONFIG1-B
91 h
Bit 7
Bit 6
Bit Name LOF1 LOF0
Reset
1
0
Value
R/W
R/W
0=
304–434 304–315
1=
315–916 434–916
0Eh CONFIG2-B
10 h
Bit 7
Bit 6
Bit Name DSREF FRM
Reset
0
0
Value
R/W
R/W
0=
Fixed
Friendly
1=
Adaptive Direct
0Fh CONFIG3-B
30 h
Bit 7
Bit 6
Bit Name AFF1 AFF0
Reset
0
0
Value
R/W
R/W
0=
0.5–1 0.5–2
kHz
kHz
1=
2–4 kHz 1–4 kHz
10h COMMAND-B 9 h
Bit 7
Bit 6
Bit Name AFFC IFLA
Reset
0
0
Value
R/W
R/W
0=
AFFx
No
OFF
1=
AFFx ON –20 dB
11h F1-B
4800 h
Bit 7
Bit 6
Bit Name —
—
Reset
0
1
Value
R/W
R/W
12h F2-B
0h
Bit 7
Bit 6
Bit Name F7
F6
Reset
0
0
Value
R/W
R/W
Bit 5
CF1
0
Bit 4
CF0
1
R/W
315–434
868
R/W
314
434–868
Bit 5
MODU
0
Bit 4
DR1
1
R/W
OOK
FSK
R/W
2.4–4.8
9.6–19.2
Bit 5
OLS
1
Bit 4
LVDS
1
R[A]
RAS
RR[A]
RAS
Unlocked Low V
Bit 5
—
0
R/W
RX
TX
Bit 4
RSSIE
0
R/W
No
Yes
Bit 5
—
0
R/W
Bit 4
—
0
R/W
Bit 5
F5
0
R/W
Bit 4
F4
0
R/W
Bit 3
—
0
R
—
—
Bit 2
SL
0
R/W
T/R
R/T
Bit 3
DR0
0
Bit 2
TRXE
0
R/W
2.4–9.6
4.8–19.2
R/W
Standby
Enable
Bit 3
ILA1
0
Bit 2
ILA0
0
R/W
0–8 dB
R/W
0–14 dB
14–24 dB 8–24 dB
Bit 3
EDD
1
Bit 2
RAGC
0
R/W
R/W
Slow dec. No
Fast dec. Yes
Bit 3
F11
1
R/W
Bit 2
F10
0
R/W
Bit 3
F3
0
R/W
Bit 2
F1
0
R/W
Bank B Registers
Bit 1
LVDE
0
R/W
No
Yes
Bit 0
CLKE
1
R/W
No
Yes
Bit 1
DME
0
R/W
No
Yes
Bit 0
SOE
0
R[A]
No
Yes
Bit 1
—
0
Bit 0
—
0
R/W
0–8 dB
R/W
0–14 dB
14–24 dB 8–24 dB
Bit 1
FAGC
0
R/W
No
Yes
Bit 0
BANKS
1
R[A]
B Bank
A Bank
Bit 1
F9
0
R/W
Bit 0
F8
0
R/W
Bit 1
F1
0
R/W
Bit 0
F0
0
R/W
Figure 33. Bank Registers