MC33596_10 Datasheet, PDF (10/70 Pages) Freescale Semiconductor, Inc – PLL Tuned UHF Receiver for Data Transfer Applications

State Machine
Table 5. Serial Digital Interface Feature versus Selected Mode
Selected Mode
MC33596 Digital Interface Use
Configuration
Receive DME = 1
DME = 0
Standby / LVD
SPI slave, data received on MOSI, SCLK from MCU, MISO is output (SEB=0)
SPI master, data sent on MOSI with clock on SCLK (SEB=0)
SPI deselected, received data are directly sent to MOSI (SEB=0)
SPI deselected, all I/O are high impedance (SEB =1)
Refer to Section 10, “State Machine,” and to Figure 2 for more details about all the conditions that must
be complied with in order to change between two selected modes.
The data transfer protocol for each mode is described in the following section.
10 State Machine
This section describes how the MC33596 controller executes sequences of operations, relative to the
selected mode. The controller is a finite state machine, clocked at T_digclk. An overview is presented in
Figure 2 (note that some branches refer to other diagrams that provide more detailed information).
There are three different modes: configuration, receive, and standby/LVD. Each mode is exclusive and can
be entered in different ways, as follows.
• External signal: CONFB for configuration mode
• External signal and configuration bits: CONFB and TRXE for all other modes,
• External signal and internal conditions: see Figure 3 and Figure 12 for information on how to
enter standby/LVD mode
After a Power-on Reset (POR), the circuit is in standby mode (see Figure 2) and the configuration register
contents are set to the reset value.
At any time, a low level applied to CONFB forces the finite state machine into configuration mode,
whatever the current state. This is not always shown in state diagrams, but must always be considered.
Refer to (Section 14, “Power-On Reset and MC33596 Startup”) for timing sequence between standy mode
and configuration mode.
MC33596 Data Sheet, Rev. 4
10
Freescale Semiconductor