MC33596_10 Datasheet, PDF (36/70 Pages) Freescale Semiconductor, Inc – PLL Tuned UHF Receiver for Data Transfer Applications

Register Description
• Low-pass average filter generating the data slicer reference, if DSREF is set
• Data manager
Table 10. Base Band Parameter Configuration
DR1 DR0
0
0
0
1
1
0
1
1
Data Filter
Cut-off Frequency
6 kHz
12 kHz
24 kHz
48 kHz
Average Filter
Cut-off Frequency
0.5 kHz
1 kHz
2 kHz
4 kHz
Data Manager
Data Rate Range
2–2.8 kBd
4–5.6 kBd
8–10.6 kBd
16–22.4 kBd
If the data manager is disabled, the incoming signal data rate must be lower than or equal to the data
manager maximum data rate.
TRXE (Receiver Enable) enables the whole receiver. This bit must be set to high level if MCU wakes the
MC33956 to enter receive mode.
0 = standby mode
1 = other modes can be activated
DME (Data Manager Enable) enables the data manager.
0 = disabled
1 = enabled
SOE (Strobe Oscillator Enable) enables the strobe oscillator.
0 = disabled
1 = enabled
Figure 26 describes configuration register 3, CONFIG3.
Bit Name
Reset Value
Access
Bit 7
AFF1
0
R/W
Bit 6
AFF0
0
R/W
Bit 5
Bit 4
Bit 3
Bit 2
OLS
LVDS
ILA1
ILA0
1
1
0
0
R
R
R/W
R/W
Figure 26. CONFIG3 Register
Bit 1
—
0
—
Bit 0
—
0
—
Addr
$02
OLS (Out of Lock Status) indicates the current status of the PLL.
0 = The PLL is in lock-in range
1 = The PLL is out of lock-in range
LVDS (Low Voltage Detection Status) indicates that a low voltage event has occurred when LVDE = 1.
This bit is read-only and is cleared after a read access.
0 = No low voltage detected
1 = Low voltage detected
ILA[1:0] (Input Level Attenuation) define the RF input level attenuation.
MC33596 Data Sheet, Rev. 4
36
Freescale Semiconductor