MC33596_10 Datasheet, PDF (41/70 Pages) Freescale Semiconductor, Inc – PLL Tuned UHF Receiver for Data Transfer Applications

Register Description
Table 18. ID Length Selection
IDL1
0
0
1
1
IDL0
0
1
0
1
ID Length
2 bits
4 bits
5 bits
6 bits
ID[5:0] (Identifier) sets the identifier. The ID is Manchester coded. Its LSB corresponds to the register’s
LSB, whatever the specified length.
Figure 31 defines the Header register, HEADER.
Bit Name
Reset Value
Access
Bit 7
HDL1
1
R/W
Bit 6
HDL0
0
R/W
Bit 5
Bit 4
Bit 3
Bit 2
HD5
HD4
HD3
HD2
0
0
0
0
R/W
R/W
R/W
R/W
Figure 31. HEADER Register
Bit 1
HD1
0
R/W
HDL[1:0] (Header Length) sets the length of the header, as shown on Table 19.
Table 19. Header Length Selection
HDL1
0
0
1
1
HDL0
0
1
0
1
HD Length
1 bits
2 bits
4 bits
6 bits
Bit 0
HD0
0
R/W
Addr
$0B
HD[5:0] (Header) sets the header. The header is Manchester coded. Its LSB corresponds to the register’s
LSB, whatever the specified length.
16.6 RSSI Register
Figure 32 describes the RSSI Result register, RSSI.
Bit Name
Reset Value
Access
Bit 7
RSSI7
0
R
Bit 6
RSSI6
0
R
Bit 5
Bit 4
Bit 3
RSSI5
RSSI4
RSSI3
0
0
0
R
R
R
Figure 32. RSSI Register
Bit 2
RSSI2
0
R
Bit 1
RSSI1
0
R
Bit 0
RSSI0
0
R
Addr
$0C
Bits RSSI[7:4] contain the result of the analog-to-digital conversion of the signal measured at the LNA
output.
MC33596 Data Sheet, Rev. 4
Freescale Semiconductor
41