MC33596_10 Datasheet, PDF (26/70 Pages) Freescale Semiconductor, Inc – PLL Tuned UHF Receiver for Data Transfer Applications

Configuration Mode
13 Configuration Mode
13.1 Description
This mode is used to write or read the internal registers of the MC33596.
As long as a low level is applied to CONFB and a high level to STROBE (see Figure 2), the MCU is the
master node driving the SCLK input, the MOSI line input, and the MISO line output. Whatever the
direction, SPI transfers are 8-bit based and always begin with a command byte, which is supplied by the
MCU on MOSI. To be considered as a command byte, this byte must come after a falling edge on CONFB.
Figure 18 shows the content of the command byte.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
N1
N0
A4
A3
A2
A1
A0
R/W
Figure 18. Command Byte
Bits N[1:0] specify the number of accessed registers, as defined in Table 7.
Table 7. Number N of Accessed Registers
N[1:0]
00
01
10
11
Number N of Accessed Registers
1
2
4
8
Bits A[4:0] specify the address of the first register to access. This address is then incremented internally
by N after each data byte transfer.
R/W specifies the type of operation:
0 = Read
1 = Write
Thus, this bit is associated with the presence of information on MOSI (when writing) or MISO (when
reading).
Figure 19 and Figure 20 show write and read operations in a typical SPI transfer. In both cases, the SPI is
a slave. A received byte is considered internally on the eighth falling edge of SCLK. Consequently, the last
received bits, which do not form a complete byte, are lost.
Refer to Section 19.8, “Digital Interface Timing,” to view the timing definition for SPI communication.
If several SPI accesses are done, a high and low level is applied to CONFB, and so on. By applying a high
level to STROBE, the MC33596 never enters standby mode. If there is no way to configure the level on
STROBE, the time interval between two SPI accesses must be less than one digital clock period T_digclk.
MC33596 Data Sheet, Rev. 4
26
Freescale Semiconductor